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AR# 70479

AXI Bridge for PCI Express Gen3 - FAQs and Debug Checklist


This answer record provides FAQs and Debug Checklist for AXI Bridge for PCI Express Gen3 IP. For FAQs and Debug Checklist on general PCIe issues, not related specific to this IP, please refer to (Xilinx Answer 69751)

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express




Debug Checklist:


  • The AXI Bridge IP uses PCIe Base IP and GT similarly to the regular PCIe Integrated IP.
    If there are issues related to link up, enumeration, general PCIe boot-up, or a detection issue, see (Xilinx Answer 69751) as it will have nothing to do with the AXI MM Bridge portion.

  • Probe the M_AXI and S_AXI interfaces (depending on the direction of the data flow you are debugging) and see if you can trigger / catch the request you have made.
    If the packet shows up in here, check the address field (ARADDR for Read Request or AWADDR for Write Request) to ensure that the address is in the expected AXI Address (after translation) for this request.

  • The AXI Translation vector is at the C_PCIEBAR2AXIBAR_# parameter and the C_PCIEBAR2AXIBAR_# parameter. The AXI BAR settings is at the C_AXIBAR_# parameter

  • If the M_AXI and S_AXI interfaces do not show anything, but this is not the first AXI packet prior to the failure, check previous AXI transaction and make sure that they have completed.
    For Writes you must see a corresponding BRESP, BVALID, and BREADY for each request. For Reads you must see a corresponding RRESP, RVALID, and RREADY for each request.
    If there is any packet that has not completed (check both the Writes and Reads interfaces), investigate those first before moving on.
    PCIe has a strict packet ordering rule and that pending request might have halted the data pipeline.

  • If the M_AXI and S_AXI interfaces do not show anything, and this is the first AXI packet prior to the failure (or there is no other pending transaction), then check the following:
    • The Bridge Enable bit in the Bridge Control Register (Offset 0x148 on s_axil_* AXI Lite interface) must be set to 1 before any data can flow through
    • Check AXIS_RQ/CQ/CC/RC (for AXI MM Gen3 IP) and see if you can spot the packet there.
    • If it is visible in the AXIS* interface, then the problem is in the Bridge. For AXI MM Gen3, you must obtain internal debug probes (encrypted IP). 

Additional Debug Info: Please refer to 'Appendix B: Debugging' of (PG194) AXI Bridge for PCI Express Gen3 Subsystem

Revision History:

04/18/2018 : Initial Release

AR# 70479
Date 04/18/2018
Status Active
Type General Article
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