UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 70481

DMA Subsystem for PCI Express - FAQs and Debug Checklist

Description

This answer record provides FAQs and a Debug Checklist for the DMA Subsystem for PCI Express IP. 

For FAQs and Debug Checklist on general PCIe issues, not related specifically to this IP, please refer to (Xilinx Answer 69751).


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

FAQs:

NA

Debug Checklist:

  • DMA uses PCIe Base IP and GT similar to the regular PCIe Integrated IP.
    If there are issues related to link up, enumeration, general PCIe boot-up, or a detection issue, please follow the PCIe debug strategy as described in (Xilinx Answer 69751) as it will have nothing to do with the AXI.

  • Missing interrupts - See (Xilinx Answer 69751)

  • Driver fails to load
    • Set the XDMA_DEBUG directive to 1 in the xdma-core.c and xdma-core.h file and recompile the driver. Then check the output of the dmesg command to help you narrow down where the issue is.
    • Once you have narrowed down to which function calls it fails, do a PIO transfer to read or write to the particular register that the driver is accessing to see what response you get.
    • The primary section to look for is the probe function inside of the xdma-core.c file.
      This probe function is called when you insert the driver into the Kernel and will read various DMA status registers to indicate which features are available and set an Initialization value to it
  • Hang / Kernel Panic / Unexpected Reboot at Runtime - See (Xilinx Answer 69751)

  • Lower than expected performance
    • Check the Link Status in lspci to ensure that your link is coming up to the full speed and width                                                                   
    • Check Max Payload Size and Max Read Request Size using lspci. Some systems might only support 128 Byte transfer which will be slower than 256 Byte or 512 Byte capable systems
    • Generally, larger transfer per descriptor will result in higher performance, but it can also be caused by system limitations or AXI peripherals behind the XDMA IP.
  • XDMA driver hangs when doing C2H streaming transfer
    • Check by loading the driver into the kernel by enabling the descriptor "credit based". Modify the Insmod command in the load_driver.sh file as follows before sourcing it.
      • insmod ../driver/xdma.ko enable_credit_mp=1

Additional Debug Info:

Please refer to 'Appendix C: Debugging' of (PG195) DMA/Bridge Subsystem for PCI Express.

https://www.xilinx.com/support/documentation-navigation/see-all-versions.html?xlnxproducttypes=IP%20Cores&xlnxipcoresname=dma-subsystem-pcie

Revision History:
04/01/2018 : Initial Release

AR# 70481
Date 08/13/2018
Status Active
Type General Article
IP
Page Bookmarked