AR# 70483

UltraScale+ PCI Express Integrated Block - FAQs and Debug Checklist


This answer record provides FAQs and a Debug Checklist for UltraScale+ PCI Express Integrated Block IP. 

For FAQs and a Debug Checklist on general PCIe issues, not related specifically to this IP, please refer to (Xilinx Answer 69751).

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express



Q) Which Data Alignment option should be used for better performance?

A) For performance critical applications, Dword Aligned mode should be used instead of Address-Aligned mode.

Debug Checklist:

See (Xilinx Answer 69751)

LCRC error on our bus analyzer (or in AER); after a NAK, the replay goes through correctly

If you are seeing an LCRC error on the bus analyzer, .several conditions can cause this:

  • User logic error
  • Tready and Tvalid out of sync
  • Deassertion of Tvalid as an attempt to throttle
  • Incorrect TKEEP
  • SOP/EOP not used correctly on Tuser (for straddle)
  • Premature TLAST

With a link analyzer, you will see that often the core will send an EDB Ordered Set (0xC0C0C0C0 in PCIe Gen3) to invalidate the packet.

The next packet in the queue is what will be on replay, if the link partner does not accept / see the EDB and sends a NAK on the packet.

Other symptoms you might observe in the trace:

  • Recovery cycle of the link after the packet
  • Secondary packet of unknown type, bad length
  • Data repeated over and over, or zero-padding in the actual packet

To debug this issue further, add an ILA at the offending stream interface (based on packet type) and trigger on LTSSM being in Recovery.rcvrcfg.

Place the trigger late in the trace window, and you should be able to capture the bad packet at the user interface.

Additional Debug Info:

Please refer to 'Appendix c: Debugging' of (PG213) UltraScale+ Devices Integrated Block for PCI Express

Revision History:

04/18/2018 : Initial Release

AR# 70483
Date 07/03/2018
Status Active
Type General Article