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AR# 70485

UltraScale+ GTH/GTY - how to update CPLL calibration settings during a rate change

Description

The GTH/GTY of UltraScale+ enables a block called the CPLL Calibration Block. 

This block is needed to reliably lock in the following circumstances.

  • After configuration
  • When removing/re-applying reference Clock
  • When asserting/de-asserting CPLLPD

When the CPLL has to support dynamic line rate switching, it is requested to manage some ports of the Calibration Block.

The following ports of the Calibration Block should be handled during rate change:

GTH case:

gtwiz_gthe4_cpll_cal_bufg_ce_in

gtwiz_gthe4_cpll_cal_cnt_tol_in

gtwiz_gthe4_cpll_cal_txoutclk_period_in


GTY case:

gtwiz_gtye4_cpll_cal_bufg_ce_in

gtwiz_gtye4_cpll_cal_cnt_tol_in

gtwiz_gtye4_cpll_cal_txoutclk_period_in


These ports are not automatically exposed for customization.

Solution

CPLL Rate Changing in the GT Wizard Example Design:

  • Configure the GT by using the UltraScale Transceiver Wizard.
    • Once the GT is configured in the Tcl Console, execute the below command.
      This enables the calibration block to expose the required ports up to the top-level of the example design:
set_property -dict [list CONFIG.INCLUDE_CPLL_CAL {1} ] [get_ips gtwizard_ultrascale_0]
    • select the XCI of the GT and right click to run Reset Output Products.
    • Run Generate Output Products or Open IP Example Design to generate the example design.
  • The top-level of the example design is generated with the following signals. (see (PG182) the values here are just an example)
wire [17:0] hb0_gtwiz_gthe4_cpll_cal_txoutclk_period_int = 18'b00000000000000000000111110100000;
wire [17:0] hb0_gtwiz_gthe4_cpll_cal_cnt_tol_int = 18'b00000000000000000000000000101000;
wire [0:0] hb0_gtwiz_gthe4_cpll_cal_bufg_ce_int = 1'b1; 
  • The signal connected to the bufg_ce can be left to 1.
    The other two signals should be connected and set properly as per page 66 in (PG182) in order to manage the different CPLL rate.
    See the example below.

Example of CPLL rate change implementation:


 

CPLL Rate Changing in IP:

  • When the Transceiver is part of an IP, this flow is recommended to expose the Calibration Block ports:
  • Example for 1G/2.5G Ethernet PCS/PMA or SGMII.
    1. Configure the IP and in Shared Logic select GT in Example Design.
    2. Generate the example design with Open IP Example Design

 


  • Open the Example Design
    • In the window Sources, it is possible to see the name of the XCI of the GT
    • In the Tcl console execute the following:
set_property -dict [list CONFIG.INCLUDE_CPLL_CAL {1} ] [get_ips gig_ethernet_pcs_pma_0_gt]

 


 
    • In the windows Sources select the XCI of the GT and right click to run Reset Output Products and Generate Output Products.
  • The files of the example design are not re-generated. The ports of the  calibration block have to be included manually.
  • The file that instantiates the GT is the gig_ethernet_pcs_pma_0_support.v
    • The following ports should be added:

.gtwiz_gthe4_cpll_cal_txoutclk_period_in (cpll_cal_txoutclk_period_in),  

.gtwiz_gthe4_cpll_cal_cnt_tol_in (cpll_cal_cnt_tol_in),

.gtwiz_gthe4_cpll_cal_bufg_ce_in (1'b1)

  • Connect the ports cpll_cal_txoutclk_period_in and cpll_cal_cnt_tol_in to valid values in order to manage the CPLL dynamic line rate switching.

The table below shows an example to support the CPLL rate at 1 Gbps and 2.5 Gbps with an input reference clock of 156.25 MHz and free running clock of 50MHz. 

See also the example above.

1G2.5G
cpll_cal_txoutclk_period18'b0000000000000000001001110001000018'b00000000000000000011000011010100
cpll_cal_cnt_tol18'b0000000000000000000000000110010018'b00000000000000000000000001111101
AR# 70485
Date 02/09/2018
Status Active
Type General Article
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