AR# 70504


Zynq UltraScale+ PL programming might fail with the message "FPGA fail to get the done status" in xilfpga library and FSBL.


PL programming can be done in the FSBL, u-boot and Linux. 

In u-boot and Linux, an IPI request is sent to the PMU, and the PMUFW will use the xilfpga library to copy the bitstream to the PCAP with CSU_DMA..

Before the CSU_DMA transfer to the PCAP, the xilfpga library resets the PL and the PS_INIT_B is set to a low level. 

The xilfpga library polls the PCAP status register to decide if PL initialization has completed. 

Normally, PS_INIT_B also goes to a high level when the PL init has completed.

In some cases, PS_INIT_B takes a long time to increase to a high level because of capacitive load.

For example:


When the triode is removed, the rising edge of the PS_INIT_B is about 300ns. 

If the triode is there, the rising edge is several microseconds. 

When PS_INIT_B is low, software should not start the CSU_DMA transfer to the PCAP. 

Otherwise, xilfpga will fail with the message "FPGA fail to get the done status". 

According to (UG1085), PS_INIT_B should not be held Low externally to delay the PL configuration sequence because the signal level is not visible to software.


Normally, the rising edge of PS_INIT_B is about several hundred nanoseconds.

If the rising edge is measured and is much more than the normal value, we can add some delay between the PL reset and CSU_DMA transfer to PCAP in the xilfpga code. 

There is big change in the xilfpga code between the 2018.3 and 2019.1 versions, so we can add the delay in three different ways for the 2018.3, 2019.1 and previous versions.

1) In 2018.2 and previous versions, we can add some delay between XFpga_PcapInit(flags) and XFpga_WriteToPcap(WrSize, WrAddrHigh, WrAddrLow) in XFpga_PL_BitStream_Load() in "xilfpga_pcap.c". 

The "xilfpga_pcap.c" file is in the PMUFW BSP. 

2) In 2018.3, we can add some delay between XFpga_PL_Preconfig() and XFpga_PL_WriteToPl() in XFpga_PL_BitStream_Load() in "xilfpga.c".

 The "xilfpga.c" file is in the PMUFW BSP. 

3) In 2019.1, we can add some delay between XFpga_PL_Preconfig() and XFpga_PL_Write() in XFpga_PL_BitStream_Load() in "xilfpga.c".

The "xilfpga.c" file is in the PMUFW BSP.

You can insert a large delay first to test if it works, and then decrease the delay after more testing.

The FSBL contains similar code to the xilfpga library to program the PL. 

This issue can also happen in the FSBL if the rising edge takes a very long time.

AR# 70504
Date 07/23/2019
Status Active
Type General Article
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