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AR# 70553

7 Series Integrated Block for PCIe (Vivado 2017.4) - user_reset_out (active-high) is connected to the rst_n (active-low) input of the pcie_7x_0_tandem_cpler module

Description

When the Integrated block for PCIe IP is generated with the "Tandem PROM" option, it is found that the pcie_7x_0_tandem_cpler module is put in reset.

This is because the user_reset_out (active-high) is connected to the rst_n (active-low) input of the pcie_7x_0_tandem_cpler module.

Solution

To resolve this issue you will need to update this connectivity manually to invert the signal. 

This issue has been fixed in Vivado 2018.1.

Revision History:

04/30/2018 - Initial Release

AR# 70553
Date 04/30/2018
Status Active
Type General Article
Devices
Tools
IP
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