When the Integrated block for PCIe IP is generated with the "Tandem PROM" option, it is found that the pcie_7x_0_tandem_cpler module is put in reset.
This is because the user_reset_out (active-high) is connected to the rst_n (active-low) input of the pcie_7x_0_tandem_cpler module.
To resolve this issue you will need to update this connectivity manually to invert the signal.
This issue has been fixed in Vivado 2018.1.
04/30/2018 - Initial Release