Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices?
When using the MIPI D-PHY RX IP (or MIPI CSI-2 Receiver Subsystem) targeting UltraScale+ device, users can experience SoT/ECC/CRC errors on some of the UltraScale+ devices, even when the image-sensor seems to have the correct Global operation timing parameters set.
This issue is reported with the MIPI D-PHY RX IP (or MIPI CSI-2 Receiver Subsystem) when the IP is generated using Vivado 2017.2, 2017.3 and 2017.4.
This issue occurs on some devices, when the image-sensor is set to non-continuous clock mode.
(No issue is observed when the image-sensor is set to Continuous clock mode).
The Fluctuating input signal of the MIPI D-PHY clock lane during the LP --> HS mode transition can trigger the capture of some invalid data in data lane FIFO which lead to SoT/ECC/CRC errors.
This issue will be fixed in Vivado 2018.1.