AR# 70591

LogiCORE IP MIPI D-PHY v4.0 - Can I change IDELAY tap values on the fly for MIPI D-PHY IP v4.0? (IP targeting 7 Series devices)

Description

Can I changes the tap values of IDELAY on the fly for MIPI D-PHY IP v4.0 manually to fit user system requirements?

Solution

Yes, you can, if you are using a MIPI D-PHY IP targeting 7 Series devices.

 

  • Vivado 2017.3 - Users can download the MIPI D-PHY IP and MIPI CSI-2 RX Subsystem patch from (Xilinx Answer 70195) to enable this feature.
  • Vivado 2017.4 - Please use IP generated by Vivado 2018.1 and later.
  • Vivado 2018.1 - This feature is a standard feature in the MIPI D-PHY LogiCORE IP in Vivado 2018.1 and later.

"Dynamic tap setting per lane" capability is available in Fixed calibration mode only.

The MIPI D-PHY IP register interface must be enabled to access this feature.

New register added for this feature:

0x4 D-PHY RX Parameter configuration 32-bit R/W To Programing Tap values in Fixed mode of calibration

 

Bits Name Access Default Value Description
31:29 Reserved R/W 0 Reserved
28:24 Tap value for lane3 R/W IDELAY Tap Value from GUI Programs IDELAY Tap value for lane3
23:21 Reserved R/W 0 Reserved
20:16 Tap value for lane2 R/W IDELAY Tap Value from GUI Programs IDELAY Tap value for lane2
15:13 Reserved R/W 0 Reserved
12:8 Tap value for lane1 R/W IDELAY Tap Value from GUI Programs IDELAY Tap value for lane1
7:5 Reserved R/W 0 Reserved
4:0 Tap value for lane0 R/W IDELAY Tap Value from GUI Programs IDELAY Tap value for lane0

Notes:

  1. Tap values can programed dynamically during the core operation. You are not required to disable the core to program a different tap value.
  2. the Initial value for the tap values for all lanes will be the same as value selected from the GUI [IDELAY Tap Value]
  3. Reserved bits are R/W. These reserved bits can be written with a non-zero value but only the required 5-bits will be used for tap programming.
  4. To run any simulation/example design using the patch, you must recompile the patch code.
    You can use the following Command to allow Vivado to re-compile local cores:

 

set_property sim.use_ip_compiled_libs 0 [current_project]

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AR# 70591
Date 04/09/2018
Status Active
Type General Article
Devices More Less
Tools
IP