AR# 70657

2017.4 40G/50G Ethernet Subsystem - 40G 256-bit AXI Stream Interface Example Design sometimes does not work in hardware

Description

When using the 40G 256-bit AXI Interface, both the RX and TX AXI Stream interfaces are clocked with the rx_core_clk input.

However, the example design is using separate clocks for the TX packet generator and RX packet monitor. This can result in data errors when running the example design in Hardware.

Note: his Answer Record does not apply to the 128-bit AXI Stream interface for the 40/50G Ethernet Subsystem. The 128-bit AXI Steam Interface has a different clocking structured detailed in (PG211) and is not affected by this issue.

Solution

Option 1:

To resolve this issue in Vivado 2017.4, if the "Include FIFO" option has been selected in the GUI:

The AXI Steam interface clock and example design packet generator/monitor clocks can be changed to all be clocked with tx_clk_out by changing the top level _exdes.v file assignment from the following:

assign rx_core_clk_0 = rx_clk_out_0;

Change to the following:

assign rx_core_clk_0 = tx_clk_out_0;

Option 2:

To resolve this issue in Vivado 2017.4, if the "Include FIFO" option has not been selected in the GUI:

The AXI Steam interface clock and example design packet generator/checker clocks can be changed to all be clocked with rx_clk_out by changing the top level _exdes.v file assignment from the following:

l_ethernet_0_pkt_gen_mon #(
.PKT_NUM (PKT_NUM))
 i_l_ethernet_0_pkt_gen_mon_0
(
    .gen_clk (tx_clk_out_0),
    .mon_clk (rx_core_clk_0),

Change to the following:

l_ethernet_0_pkt_gen_mon #(
.PKT_NUM (PKT_NUM))
 i_l_ethernet_0_pkt_gen_mon_0
(
    .gen_clk (rx_core_clk_0),
    .mon_clk (rx_core_clk_0),

AR# 70657
Date 03/12/2018
Status Active
Type General Article
IP