Some configurations of the DFT IP core might be logically incorrect following Synthesis when Vivado 2018.1 is used and synchronous reset is not present.
This will manifest as mismatches versus behavioral simulation on all core outputs.
The work-around is to ensure the Synchronous Reset (SCLR) core option is checked before generating the IP core.
This issue will be fixed in Vivado 2018.2. It is recommended to use Vivado 2017.4 or the above work-around as alternatives.