UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 70699

2018.1 Vivado IP Release Notes - All IP Change Log Information

Description

This Answer Record contains a comprehensive list of IP change log information from Vivado 2018.1 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

(c) Copyright 2018 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.

 

100M/1G TSN Subsystem (2.0)

* Version 2.0

* Feature Enhancement: Learning, Aging Switch features implemented

* Feature Enhancement: Moved to HIP flow

* Revision change in one or more subcores

10G Ethernet MAC (15.1)

* Version 15.1 (Rev. 5)

* Bug Fix: Fixed corner case TX issue: Under some circumstances the core locks-up at power-on

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 12)

* Bug Fix: Waiting for RX block lock to occur before sending packets from TB on TX XGMII Interface.

* Revision change in one or more subcores

10G Ethernet Subsystem (3.1)

* Version 3.1 (Rev. 8)

* General: Updated licensing for the core. The core will now inherit licenses of sub-cores

* Revision change in one or more subcores

10G/25G Ethernet Subsystem (2.4)

* Version 2.4

* Bug Fix: Updated example design files for

* Bug Fix: Updated clock domain for

* Bug Fix: Corrected timestamp connections when MAC+PCS BASER core generated for 2-step PTP, see AR70659

* Feature Enhancement: Added header files for

* Feature Enhancement: Added PCS/PMA 32 bit variant to build

* Feature Enhancement: Adding 802.1cm preemption feature for

* Feature Enhancement: Added MAC+PCS/PMA 32-bit 1step support

* Feature Enhancement: For Ethernet MAC-64 variant clk port removed and added tx_core_clk and rx_core_clk

* Revision change in one or more subcores

1G/10G/25G Switching Ethernet Subsystem (2.0)

* Version 2.0

* Feature Enhancement: Added 1G/10G/25G switching support for 64bit MAC+PCS/PMA 25G core for GTY3/GTY4 devices

* Feature Enhancement: Added 1G/10G switching support for 32b PCS/PMA only core

* Feature Enhancement: Added support for GT in Core / Example design and GT status and control ports

* Feature Enhancement: Added multicore (4-core) support to switch between 1G/10G/25G

* Feature Enhancement: Updated the clocking structure to reduce the clk-wiz utilization

* Feature Enhancement: Added device support for Virtex UltraScale GTY, Kintex UltraScale GTY, Kintex UltraScale+ GTY, Zynq UltraScale+ GTY

* Revision change in one or more subcores

1G/2.5G Ethernet PCS/PMA or SGMII (16.1)

* Version 16.1 (Rev. 3)

* Bug Fix: Fixed the lvds refclk selection based on sync and async clock configuration in the GUI

* Bug Fix: Updated the REFCLK pin frequency for IDELAYE2 based on the input clock

* Revision change in one or more subcores

32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 10)

* Added support for xc7z015-clg485 device and package

* Fixed placer errors: '[30-574] - Poor Placement for routing between an IO pin and BUFG...' For this, added set_property CLOCK_DEDICATED_ROUTE FALSE constraint in xdc file

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 15)

* Revision change in one or more subcores

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 14)

* Revision change in one or more subcores

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 13)

* Revision change in one or more subcores

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 16)

* Revision change in one or more subcores

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 13)

* Revision change in one or more subcores

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 14)

* Revision change in one or more subcores

40G/50G Ethernet Subsystem (2.3)

* Version 2.3 (Rev. 2)

* Bug Fix: Updated example design files for fixes

* Bug Fix: Updated clocking for 256-bit Regular AXI4-Stream datapath interface for 40G speed

* Feature Enhancement: Added .h (Header) file for AXI4-Lite registers

* Revision change in one or more subcores

64-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 10)

* Added support for xc7z015-clg485 device and package

* Fixed placer errors: '[30-574] - Poor Placement for routing between an IO pin and BUFG...' For this, added set_property CLOCK_DEDICATED_ROUTE FALSE constraint in xdc file

7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 9)

* General: Added support for xa7a12tcpg238, xa7a12tcsg325, xa7a25tcpg238 and xa7a25csg325 Artix-7 devices.

7 Series Integrated Block for PCI Express (3.3)

* Version 3.3 (Rev. 8)

* General: Added support for xa7a12t(cpg238,csg325) and xa7a25t(cpg238,csg325) devices

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 13)

* No changes

AMM Master Bridge (1.0)

* Version 1.0 (Rev. 2)

* Feature Enhancement: Reduced the resource count

* Feature Enhancement: Updated the arbitration logic

* Revision change in one or more subcores

AMM Slave Bridge (1.0)

* Version 1.0 (Rev. 6)

* General: Updated the ID WIDTH parameter and the visibility of ID ports based on the ID width

* Revision change in one or more subcores

AXI 1G/2.5G Ethernet Subsystem (7.1)

* Version 7.1 (Rev. 3)

* Bug Fix: configuration_vector input is connected with the value as per the AN enablement configuration

* Bug Fix: systemtimer_clk input is driven from the example design and it is with the value configured in the GUI

* Bug Fix: For UltraScale/UltraScale+ devices, attribute REFCLK_FREQUENCY is passed through XDC to TEMAC core

* Feature Enhancement: Added .h header file for AXI4 lite register information

* Feature Enhancement: IPI design block automation connects the mii/gmii/rgmii/sgmii/sfp along with mdio and phy_rst_n ports based on the board/part selected

* Other: Refer to tri_mode_ethernet_mac v9_0 and gig_ethernet_pcs_pma v16_1 core change logs for changes in the sub cores of this core

* Revision change in one or more subcores

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 14)

* General: Support for ID width up to 32

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 14)

* General: Updates to support address width up to 64

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 14)

* Bug Fix: Removed the address width constraint for wrap transactions as part of reducing synthesis warnings

AXI Bridge for PCI Express Gen3 Subsystem (3.0)

* Version 3.0 (Rev. 6)

* General: Fixed port width mismatches on cfg_interrupt_msix_enable, cfg_interrupt_msix_mask, cfg_interrupt_msix_vf_enable and cfg_interrupt_msix_vf_mask siganls for 7 series gen3 variant

* Revision change in one or more subcores

AXI CAN (5.0)

* Version 5.0 (Rev. 19)

* General: Updated OL path for CDC

* Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 16)

* General: Updates to example design

* Revision change in one or more subcores

AXI Chip2Chip Bridge (5.0)

* Version 5.0 (Rev. 2)

* Bug Fix: IP updated to handle interrupts more reliably

* Revision change in one or more subcores

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 15)

* New Feature: Use parameter SYNCHRONIZATION_STAGES to set the number of resync flops used in AXI4LITE async conversion, instead of constant 2.

* Revision change in one or more subcores

AXI Crossbar (2.1)

* Version 2.1 (Rev. 17)

* Revision change in one or more subcores

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 15)

* Revision change in one or more subcores

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 16)

* Revision change in one or more subcores

AXI DataMover (5.1)

* Version 5.1 (Rev. 18)

* General: Updates to example design

* General: Enhanced support for IP Integrator

* Revision change in one or more subcores

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 17)

* Feature Enhancement: Support for up to 64MB data transfer

* Revision change in one or more subcores

AXI EMC (3.0)

* Version 3.0 (Rev. 16)

* General: Register metadata added to IP

* Revision change in one or more subcores

AXI EPC (2.0)

* Version 2.0 (Rev. 19)

* General: Updated example design. No Functional changes

* Revision change in one or more subcores

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 18)

* Revision change in one or more subcores

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes

AXI EthernetLite (3.0)

* Version 3.0 (Rev. 14)

* General: Support for ID width up to 32

* Revision change in one or more subcores

AXI GPIO (2.0)

* Version 2.0 (Rev. 18)

* General: Updates to example design

* Revision change in one or more subcores

AXI HWICAP (3.0)

* Version 3.0 (Rev. 20)

* General: Updates to example design. No Functional changes

* General: IP now uses XPM FIFO

* Revision change in one or more subcores

AXI IIC (2.0)

* Version 2.0 (Rev. 19)

* General: Updated example design. No Functional changes

* Revision change in one or more subcores

AXI Interconnect (2.1)

* Version 2.1 (Rev. 17)

* Revision change in one or more subcores

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 10)

* No changes

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 4)

* No changes

AXI MMU (2.1)

* Version 2.1 (Rev. 14)

* Bug Fix: Restore parameter vector size.

* Revision change in one or more subcores

AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Memory Mapped To PCI Express (2.8)

* Version 2.8 (Rev. 8)

* Bug Fix: Fixed implementation issues for xc7z012s device. The maximum link width and speed supported for this device is x2Gen2. Refer PG055 for more details

* Other: Updated MPS value to 256 Bytes in simulation (512 Bytes is not supported by this IP)

* Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 15)

* Revision change in one or more subcores

AXI Multi Channel Direct Memory Access (1.0)

* Version 1.0 (Rev. 2)

* General: Bug fix

* General: Example design update

* Revision change in one or more subcores

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 18)

* General: Register metadata added to IP

* General: Resets to XPM FIFOs synchronized to wrclk

* Revision change in one or more subcores

AXI Protocol Checker (2.0)

* Version 2.0 (Rev. 2)

* General: Increased the MAXWAITS from 1024 to 65536

* General: Added RD/WR DECERR & SLVERR

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 16)

* Revision change in one or more subcores

AXI Protocol Firewall (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: NUM_READ_OUTSTANDING/NUM_WRITE_OUTSTANDING not always updated correctly.

* Other: Added register map

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 15)

* General: XPM migration

* Revision change in one or more subcores

AXI Register Slice (2.1)

* Version 2.1 (Rev. 16)

* New Feature: Extended Multi-SLR-crossing mode for devices with 4 SLRs.

* New Feature: Removed CE inputs to pipeline chain registers for Multi-SLR-crossing mode to improve placement flexibility.

* New Feature: Added IP-level XDC that allows aresetn to propagate as async reset to far SLRs in Multi-SLR-crossing mode.

AXI Sideband Utility (1.0)

* Version 1.0

* New Feature: Initial Release

AXI SmartConnect (1.0)

* Version 1.0 (Rev. 8)

* Bug Fix: Fixed advanced property assignment bug that prevented Exit register slice from being disabled

* Bug Fix: Fixed advanced property assignment to improve logic optimization when SUPPORTS_WRAP is set to 0

* Feature Enhancement: Enhanced low area mode automation to support more system scenarios where conversions such as clock, data width and protocol are required

* Revision change in one or more subcores

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 20)

* General: IP updated to use XPM FIFO. No Functional changes

* Revision change in one or more subcores

AXI Timebase Watchdog Timer (3.0)

* Version 3.0 (Rev. 8)

* General: Updates to example design

* Revision change in one or more subcores

AXI Timer (2.0)

* Version 2.0 (Rev. 18)

* General: Updated example design. No Functional changes

* Revision change in one or more subcores

AXI Traffic Generator (3.0)

* Version 3.0 (Rev. 2)

* General: Minor Bug fixes

* Revision change in one or more subcores

AXI UART16550 (2.0)

* Version 2.0 (Rev. 18)

* General: Updated example design. No Functional changes

* Revision change in one or more subcores

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 17)

* General: Support for ID width up to 32

* Revision change in one or more subcores

AXI Uartlite (2.0)

* Version 2.0 (Rev. 20)

* Bug Fix: SRL based shift register replaced with flop based shift register

* Other: Updated example design. No Functional changes

* Other: Enhanced support for IP Integrator

* Revision change in one or more subcores

AXI Verification IP (1.1)

* Version 1.1 (Rev. 2)

* General: updated coreinfo.yml,fix

* Revision change in one or more subcores

AXI Video Direct Memory Access (6.3)

* Version 6.3 (Rev. 4)

* General: Example design updated.

* Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 18)

* Revision change in one or more subcores

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 13)

* Feature Enhancement: AXI ID width range increased to support up to 32 bits.

* Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 13)

* General: AP_CTRL Port names modified according to original Interface. No functional changes

 

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 15)

* No changes

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 17)

* General: Upgrade to xpm_fifo for async clock conversion; removes axi_data_fifo/fifo_generator dependency.

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 14)

* No changes

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 17)

* Revision change in one or more subcores

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 15)

* General: Update internal register slice instantiation to tie-off unused input clock aclk2x.

* General: Change FSM encoding and remove unnecessary combinatorial reset tie-off on output valid/ready signals.

* General: Update initial values on register declarations to match reset values for reset-less operation.

* Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 17)

* Revision change in one or more subcores

AXI4-Stream Protocol Checker (2.0)

* Version 2.0

* New Feature: Made mark_debug attribute as optional

* New Feature: Increased the pc_status width to 32 & added axilite control interface to read registers

* New Feature: Added Sparse Tkeep programmable assertion

* New Feature: Increased the ready max wait cycles value to 65536

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 16)

* New Feature: Added Multi-SLR-crossing mode with variable pipeline stages per SLR, with IP-level XDC for internal async reset pathway.

* Other: clk_wiz update from v5.4 to v6.0

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 16)

* Bug Fix: Update all remap strings for tlast indices

* Other: Update internal register slice instantiation to tie-off unused input clock aclk2x.

* Revision change in one or more subcores

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 16)

* General: Update internal register slice instantiation to tie-off unused input clock aclk2x.

* Revision change in one or more subcores

AXI4-Stream Verification IP (1.1)

* Version 1.1 (Rev. 2)

* General: update example testbench, update interface checker for tkeep

* Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 9)

* Bug Fix: Updated YUV420 remapper to recover from early/late EOL or SOF

* Revision change in one or more subcores

Accumulator (12.0)

* Version 12.0 (Rev. 12)

* Revision change in one or more subcores

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 12)

* Revision change in one or more subcores

Aurora 64B66B (11.2)

* Version 11.2 (Rev. 4)

* Bug Fix: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection

* Other: Updated the initial value being driven in example design simulation top for PMA_INIT input

* Revision change in one or more subcores

Aurora 8B10B (11.1)

* Version 11.1 (Rev. 4)

* Bug Fix: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection

* Bug Fix: Fixed a bug that generated unexpected error messages during re-customization of IP in IP Integrator

* Other: Added support for Artix-7 XA7A12TCPG238/CSG325 and XA7A25TCPG238/CSG325 devices

* Revision change in one or more subcores

Binary Counter (12.0)

* Version 12.0 (Rev. 12)

* Revision change in one or more subcores

Block Memory Generator (8.4)

* Version 8.4 (Rev. 1)

* No changes

CANFD (1.0)

* Version 1.0 (Rev. 9)

* General: Updated example design subcore version, no functional changes

* Revision change in one or more subcores

CIC Compiler (4.0)

* Version 4.0 (Rev. 13)

* Revision change in one or more subcores

CORDIC (6.0)

* Version 6.0 (Rev. 14)

* Revision change in one or more subcores

CPRI (8.9)

* Version 8.9

* Port Change: Removed MMCM from Hard FEC implementations, now providing rsfec_clk input port (307.2MHz).

* Port Change: Added output port hyperframe_number for metrics collection.

* Bug Fix: Corrected the QPLL clock frequency on 10.1G FEC enabled line rate at 245.76MHz reference clock.

* Bug Fix: Fixed bug where xcku15p-ffva1760 and xcku15p-ffve1760 devices were not enabled for GTYE4.

* Feature Enhancement: Improved the reset input synchronization scheme.

* Feature Enhancement: Added the ability to inject bit errors in FEC enabled cores for debug.

* Feature Enhancement: Added Hard FEC support for 8.1G, 10.1G and 12.1G line rates.

* Feature Enhancement: Added Hard FEC support for MPSOC and RFSOC parts.

* Feature Enhancement: Added synchronizers to stat_cw output ports in Hard FEC Wrapper implementations.

* Feature Enhancement: Added 8b10b line rate support to the RXRECCLKOUT recovered clock port.

* Feature Enhancement: For Hard FEC implementations improved the CMAC location, transceiver location and ref clock location interaction in the CPRI GUI.

* Feature Enhancement: For UltraScale parts the watchdog timer now defaults to disabled.

* Other: Added support for Xcelium simulator.

* Revision change in one or more subcores

Chroma Resampler (4.0)

* Version 4.0 (Rev. 13)

* No changes

Clock Verification IP (1.0)

* Version 1.0 (Rev. 1)

* General: production release, added monitor, update example design testbench

Clocking Wizard (6.0)

* Version 6.0

* Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature

* Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI

* Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals.

* Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support

* Other: DRCs added for invalid input values in Override mode

 

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 14)

* No changes

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 13)

* No changes

Compact GT (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

Complex Multiplier (6.0)

* Version 6.0 (Rev. 15)

* Revision change in one or more subcores

Concat (2.1)

* Version 2.1 (Rev. 1)

* No changes

Constant (1.1)

* Version 1.1 (Rev. 4)

* Added const width and const value mismatch validation DRC

* Added support for binary data in const value field

 

Convolution Encoder (9.0)

* Version 9.0 (Rev. 13)

* Revision change in one or more subcores

DDR3 SDRAM (MIG) (1.4)

* Version 1.4 (Rev. 4)

* Bug Fix: Fixed the issue with incorrectly dumped memory voltage value in XSDB dump file

* Revision change in one or more subcores

DDR4 SDRAM (MIG) (2.2)

* Version 2.2 (Rev. 4)

* Bug Fix: Updated enablement dependency of app_wdf_data_mask and updated the same in PG150

* Revision change in one or more subcores

DDS Compiler (6.0)

* Version 6.0 (Rev. 16)

* General: Add cstring include to run_bitacc_cmodel.c to allow correct compilation with some later versions of GCC. No change to functionality.

* General: Disable unnecessary C model debug output when dithering enable. No change to functionality.

* Revision change in one or more subcores

DMA/Bridge Subsystem for PCI Express (PCIe) (4.1)

* Version 4.1

* Bug Fix: Fixed the issue with the H2C transfer where completions are not returned when odd number of bytes are being transferred (Xilinx Answer 70324)

* Bug Fix: Fixed the issue with the C2H transfer where s_axis_cc_tready signal is not asserted when odd number of bytes are being transferred (Xilinx Answer 70324)

* Bug Fix: Fixed issue with H2C transfer when 128bit axi datawidth and 64 bit address is enabled (Xilinx Answer Record - 70324)

* Bug Fix: Force overwrite PCIEBAR2AXIBAR translation vector to 0x0 is now allowed when PCIe BAR is disabled to turn off Address Translation feature in Root Port AXI Bridge mode if chosen

* Bug Fix: Fixed the issue where axi_ctl_aresetn is de-asserted before axi_clk is stable for UltraScale Plus devices

* Bug Fix: Changed the interface mode of dsc_bypass_c2h_* and dsc_bypass_h2c_* interfaces to slave

* Feature Enhancement: Added GEN4 control skip filter module with parameter(ctrl_skip_mask).This can be used for EndPoint to work with GEN4 RootPort generating control skips

* Feature Enhancement: Added ASPM L1 support for GEN3 and ASPM L0s for Gen1 & Gen2 with GUI option(in PCIe:MISC page) for Bridge Endpoint mode

* Feature Enhancement: Added a new optional dma_bridge_resetn pin that allows DMA/Bridge engine/registers to be reset without bringing PCIe link down. This can be enabled through soft_reset_en parameter

* Feature Enhancement: Added a new Interrupt Decode mode for RootPort Bridge can be enabled via Tcl parameter CONFIG.msi_rx_pin_en(true).
  Enabling this option will allow the IP to internally decode Legacy and MSI interrupt and remove the use of Interrupt FIFO. Bridge Info Register [5] is updated to reflect this change

* Feature Enhancement: Added msix_enable output port when msix is enabled

* Feature Enhancement: Added pcie_id input ports for UltraScale+ devices with parameter(pcie_id_if)

* Feature Enhancement: Rename Parity as Data Protection in GUI

* Feature Enhancement: Added Tandem XDMA support for the xczu7ev, xczu7eg, xczu7cg, xcku11p, and xcvu11p devices.

* Feature Enhancement: Added support for fsve1156, fsvg1517 packages for xczu25dr, xczu27dr, xczu28dr devices and fsvf1760 for xczu29dr device

* Other: Bridge mode Root Port only: By default, axi_ctl_aresetn now deasserts after PHY is ready (GT Initialization done)

* Other: Bridge mode Endpoint only: By default, axi_ctl_aresetn now deasserts after PCIe link is in D0_active power state (PCIe link up, configured, and enabled)

* Revision change in one or more subcores

DSP48 Macro (3.0)

* Version 3.0 (Rev. 16)

* Revision change in one or more subcores

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 14)

* Revision change in one or more subcores

Debug Bridge (3.0)

* Version 3.0 (Rev. 2)

* General: Update info message in IP GUI

* Revision change in one or more subcores

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 15)

* Revision change in one or more subcores

DisplayPort (8.0)

* Version 8.0

* Feature Enhancement: DP1.4 Update

* Revision change in one or more subcores

DisplayPort RX Subsystem (2.1)

* Version 2.1 (Rev. 2)

* Bug Fix: k7*tl device support restricted as it does not support 5.4 Gbps

* Bug Fix: App update to hide 12/16 BPC options as example design is built for 10 BPC

* Feature Enhancement: Optimized drivers released

* Feature Enhancement: With latest Video PHY, Tx buffer bypass mode uses software based MMCM programming. Please update application accordingly.

* Revision change in one or more subcores

DisplayPort TX Subsystem (2.1)

* Version 2.1 (Rev. 2)

* Bug Fix: k7*tl device support restricted as it does not support 5.4 Gbps

* Bug Fix: App update to hide 12/16 BPC options as example design is built for 10 BPC

* Feature Enhancement: Optimized drivers released

* Feature Enhancement: With latest Video PHY, Tx buffer bypass mode uses software based MMCM programming. Please update application accordingly.

* Revision change in one or more subcores

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 12)

* No changes

Divider Generator (5.1)

* Version 5.1 (Rev. 13)

* Revision change in one or more subcores

 

Double Data Rate Sampling (1.0)

* Version 1.0

* No changes

ECC (2.0)

* Version 2.0 (Rev. 12)

* No changes

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 18)

* General: Updated example design. No Functional changes

* Revision change in one or more subcores

FEC 5G Common Utilities (1.1)

* Version 1.1

* Remove hidden depth override on FIFO forcing an increase to get SRL based

* Enable pipelining to gearbox input for performance

* Add RAM initialization

* Assertions for skid buffers

* Support for split RAM when size is close to power of 2

FIFO Generator (13.2)

* Version 13.2 (Rev. 2)

* Bug Fix: Enable Safety Circuit option was unintentionally made available for user selection when Enable Reset Synchronization is not selected. This unintentional enablement is corrected and Enable Safety Circuit is available for user selection only if Enable Reset Synchronization option is selected

* Bug Fix: REQP-1839 DRC warning removed from example test bench

* Bug Fix: Read Data Count in behavioral model is updated to start with a valid value when Enable Reset Synchronization option is not selected

* Other: As FIFO Generator core uses XPM_CDC module, user must ensure that the wr_rst and rd_rst overlap for at least C_SYNCHRONIZER_STAGE+1 slowest clock cycles if Enable Reset Synchronization option is disabled

FIR Compiler (7.2)

* Version 7.2 (Rev. 11)

* Revision change in one or more subcores

Fast Fourier Transform (9.1)

* Version 9.1

* Bug Fix: C model and RTL bugfix resolving truncation noise issue manifesting in low bins for Pipelined, Streaming I/O Block Floating Point configurations. For this configuration, the pipeline latency has increased by one cycle and outputs might differ in the LSBs compared to version 9.0. No functional changes to other architectures or scaled and unscaled Pipelined, Streaming I/O configurations.

* Revision change in one or more subcores

Fibre Channel 32GFC RS-FEC (1.0)

* Version 1.0 (Rev. 6)

* General: Fix for example design mixed-language simulation issue described in (Xilinx Answer 70060).

* Revision change in one or more subcores

 

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 8)

* No changes

FlexO 100G RS-FEC (1.0)

* Version 1.0 (Rev. 6)

* General: Fix for example design mixed-language simulation issue described in (Xilinx Answer 70060).

* Revision change in one or more subcores

 

Floating-point (7.1)

* Version 7.1 (Rev. 6)

* Revision change in one or more subcores

G.709 FEC Encoder/Decoder (2.3)

* Version 2.3 (Rev. 2)

* General: Timing improvements. No change to interfaces, form or functionality.

* General: Support extended to all UltraScale+ devices

* Revision change in one or more subcores

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 15)

* General: Fixed decoder frame dropping issue.

* Revision change in one or more subcores

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 17)

* Revision change in one or more subcores

Gamma Correction (7.0)

* Version 7.0 (Rev. 14)

* No changes

Gamma LUT (1.0)

* Version 1.0 (Rev. 2)

* General: Supported devices and production status are determined automatically, to simplify support for future devices

* General: Updated synthesizable example design

* Revision change in one or more subcores

Gmii to Rgmii (4.0)

* Version 4.0 (Rev. 6)

* Bug Fix: Fix for synthesis failure where core is generated in Vivado with name gmii_to_rgmii.

* Bug Fix: Changed REFCLK_FREQUENCY of delay elements in ZUP devices to 374.953 MHz

* Bug Fix: Added synchronizers on gmii_rx_dv and gmii_rx_er to generate COL and CRS signals in gmii_clk domain.

HDCP (1.0)

* Version 1.0 (Rev. 3)

* No changes

HDCP 2.2 Cipher (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDCP 2.2 Montgomery Modular Multiplier (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDCP 2.2 Random Number Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes

HDCP 2.2 Receiver (1.0)

* Version 1.0 (Rev. 6)

* No changes

HDCP 2.2 Transmitter (1.0)

* Version 1.0 (Rev. 6)

* No changes

HDMI 1.4/2.0 Receiver (3.0)

* Version 1.1

* No changes

 

HDMI 1.4/2.0 Receiver Subsystem (3.1)

* Version 3.1

* Bug Fix: Improve transition from HDMI mode to DVI mode when no AUX packets received for 30 frames

* Bug Fix: Improved dynamic transition from HDMI 1.4 to HDMI 2.0

* Bug Fix: Fixed Native interface 4 PPC mode distribution of blanking time to be even across lines

* Bug Fix: Fixed occasional drop of audio packets

* Bug Fix: Fixed the Zynq UltraScale+ PS settings to match the demo board for FSBL support

* Feature Enhancement: Example design supporting core upversion (vid_phy_controller from v2.1 to v2.2)

* Feature Enhancement: Example design AXILITE Configuration Support (50Mhz, 100Mhz, 150Mhz, 200Mhz)

* Feature Enhancement: Example design new board supports (VCU118, ZCU104, ZCU106)

* Feature Enhancement: Example design supporting core upversion (clk_wiz from 5.4 to 6.0)

* Other: Added capability to exit deep color mode, when the sink does not receive a GCP with non-zero CD for more than 4 consecutive video fields

 

HDMI 1.4/2.0 Transmitter (3.0)

* Version 2.0

* No changes

 

HDMI 1.4/2.0 Transmitter Subsystem (3.1)

* Version 3.1

* Bug Fix: Fixed occasional color shift when using AXI4-Stream interface with YUV420 at resolutions other than UHD

* Bug Fix: Fixed occasional AXI4-Stream Bridge FIFO overflow when changing resolutions

* Bug Fix: Fixed Example Design to write out correct Zynq UltraScale+ parameters to enable FSBL for SD Card boot

* Bug Fix: Fixed sending of GCP packet during vertical blanking in deep color mode

* Bug Fix: Fixed the Zynq UltraScale+ PS settings to match the demo board for FSBL support

* Feature Enhancement: Example design supporting core upversion (vid_phy_controller from v2.1 to v2.2)

* Feature Enhancement: Example design AXILITE Configuration Support (50Mhz, 100Mhz, 150Mhz, 200Mhz)

* Feature Enhancement: Example design new board supports (VCU118, ZCU104, ZCU106)

* Feature Enhancement: Example design supporting core upversion (clk_wiz from 5.4 to 6.0)

* Other: Added AXI4-Stream Video Bridge lock to software interface to improve video lock detection

 

High Speed SelectIO Wizard (3.3)

* Version 3.3

* Bug Fix: Modified the reset logic when RIU clock is derived from PLL

* Feature Enhancement: Updated support for Async Mode (Beta)

* Feature Enhancement: Added PRBS data generators and checkers in example design

* Other: Async Mode (Beta) support is enabled for "Rx Only" Bus Direction

* Other: Async Mode (Beta) data speed is restricted to 1400Mbps (max)

* Other: Moved the PLL LOC constraint from IP XDC to Example XDC

 

I2S Receiver (1.0)

* Version 1.0

* General: First Release of IP

* General: Support for up to 8 audio channels (PCM)

* General: Supports 16/24 bits of I2S data in Master mode

* General: Supports routing of audio data amongst different channels

* General: Program and insert channel status info

I2S Transmitter (1.0)

* Version 1.0

* General: First Release of IP

* General: Support for up to 8 audio channels (PCM)

* General: Supports 16/24 bits of I2S data in Master mode

* General: Supports routing of audio data amongst different channels

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 17)

* Bug Fix: Fixed I/O pin standards issue of system clock

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 17)

* General: Updated reference clock limitation as per DS181.

* General: Added device support for XA 7A25T/7A12T parts.

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 17)

* Bug Fix: updated linerates as per ds182.

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 15)

* Revision change in one or more subcores

IBERT UltraScale GTH (1.3)

* Version 1.3 (Rev. 10)

* Bug Fix: Fixed eye scan plot issue seen with lower linerate.

* Revision change in one or more subcores

 

IBERT UltraScale GTY (1.2)

* Version 1.2 (Rev. 10)

* Feature Enhancement: Updated refclk sharing limitation for higher linerates.

* Revision change in one or more subcores

 

IEEE 802.3 200G RS-FEC (1.0)

* Version 1.0 (Rev. 2)

* General: Fix for example design mixed-language simulation issue described in AR 70060.

* Revision change in one or more subcores

IEEE 802.3 25G RS-FEC (1.0)

* Version 1.0 (Rev. 8)

* General: Fix for example design mixed-language simulation issue described in AR 70060.

* Revision change in one or more subcores

 

IEEE 802.3 400G RS-FEC (1.0)

* Version 1.0 (Rev. 2)

* General: Fix for example design mixed-language simulation issue described in AR 70060.

* Revision change in one or more subcores

IEEE 802.3 50G RS-FEC (1.0)

* Version 1.0 (Rev. 8)

* General: Fix for example design mixed-language simulation issue described in AR 70060.

* Revision change in one or more subcores

 

IEEE 802.3 Clause 74 FEC (1.0)

* Version 1.0

* General: Initial release

IEEE 802.3bj 100G RS-FEC (2.0)

* Version 2.0

* General: Added support for KP4 algorithm.

* Revision change in one or more subcores

 

ILA (Integrated Logic Analyzer) (6.2)

* Version 6.2 (Rev. 6)

* General: Updated ILA to handle XDC warnings

IOModule (3.1)

* Version 3.1 (Rev. 3)

* No changes

Image Enhancement (8.0)

* Version 8.0 (Rev. 14)

* No changes

In System IBERT (1.0)

* Version 1.0 (Rev. 6)

* General: Changed IP status from Pre-Production to Production for Kintex UltraScale+, Virtex UltraScale+ and Zynq UltraScale+.

* Revision change in one or more subcores

Interlaken 150G (2.4)

* Version 2.4

* Bug Fix: Updated OOBFC RTL for RX CRC issue on board

* Feature Enhancement: Added .h file for AXI4-register map details for

* Revision change in one or more subcores

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 12)

* Revision change in one or more subcores

JESD204 (7.2)

* Version 7.2 (Rev. 2)

* Bug Fix: Added optional transceiver debug port dmonitorclk for UltraScale and UltraScale+ devices

* Revision change in one or more subcores

JESD204 PHY (4.0)

* Version 4.0 (Rev. 2)

* Bug Fix: Corrected an issue where numerical rounding could occasionally result in an incorrect refclk frequency being set in GT when using a fractional PLL

* Bug Fix: Corrected an issue where numerical rounding could occasionally result in incorrect frequency being set on tx/rxoutclk ports in IP integrator.

* Feature Enhancement: Enabled the choice of linecoding (64B66B or 8B10B) when JESD204C standard version is chosen.

* Feature Enhancement: Modified the GT instantiation such that if the design will not use the CPLL then no CPLL CAL block will be generated for GT's that require it.

* Feature Enhancement: Added optional transceiver debug port dmonitorclk for UltraScale and UltraScale plus devices

* Feature Enhancement: Modified constraints to increased processing efficiency (No functional change)

* Revision change in one or more subcores

JESD204C (3.0)

* Version 3.0

* Bug Fix: Fixed lane enable register functionality.

* Feature Enhancement: Added 8B10B linecoding option.

* Feature Enhancement: IP Example design now generated in IP Integrator showing TX / RX sharing a JESD204_PHY and operating in loopback.

* Feature Enhancement: Removed tx/rx_tuser ports on tx/rx AXI4-Streaming interfaces. These have been replaced with discrete signals for soemb and errors.

* Feature Enhancement: Signal tx/rx_soemb now set in the cycle prior to the associated data rather than coincident with the data (see pg242 for timing diagram).

* Revision change in one or more subcores

JTAG to AXI Master (1.2)

* Version 1.2 (Rev. 6)

* General: Restricted device support for xa7s6 and xa7s15.

* Revision change in one or more subcores

 

LDPC Encoder/Decoder (2.0)

* Version 2.0

* Port Change: s_axis_ctrl_tdata and m_axis_status_tdata change from 32 to 40 bits wide when the core is configured to use the 5G New Radio (NR) standard. There are no port changes for other configurations.

* Bug Fix: PS example design fails to compile when Vivado project language is set to VHDL, AR70127

* New Feature: Support for the 5G New Radio (NR) standard

* New Feature: LDPC code tables can be initialized with LDPC codes for a given standard or with custom LDPC codes

* New Feature: Min offset scaling option

* New Feature: Optional output parity check

* New Feature: Customizable reset values for core registers

* Feature Enhancement: Optimizations to improve throughput and reduce resource utilization

* Revision change in one or more subcores

LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 14)

* No changes

LPDDR3 SDRAM (MIG) (1.0)

* Version 1.0 (Rev. 4)

* Feature Enhancement: Added XSDB_DISABLE flow for LPDDR3

* Revision change in one or more subcores

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 14)

* Revision change in one or more subcores

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 16)

* Revision change in one or more subcores

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 14)

* Revision change in one or more subcores

LTE RACH Detector (3.1)

* Version 3.1 (Rev. 2)

* Revision change in one or more subcores

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 14)

* Revision change in one or more subcores

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 9)

* No changes

MIPI CSI-2 Rx Controller (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

MIPI CSI-2 Rx Subsystem (3.0)

* Version 3.0 (Rev. 2)

* Feature Enhancement: ECC,CRC information made available on output ports for the corresponding long packets

* Feature Enhancement: Dynamic IDELAY TAP value setting in Fixed Calibration mode of 7 Series

* Other: Added support for additional 7 Series devices

* Revision change in one or more subcores

MIPI CSI-2 Tx Controller (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores

MIPI CSI-2 Tx Subsystem (2.0)

* Version 2.0 (Rev. 2)

* Feature Enhancement: Frame End Generation support from Register based Configuration

* Other: Added support for additional 7 Series devices

* Revision change in one or more subcores

MIPI D-PHY (4.1)

* Version 4.1

* Bug Fix: Fixed ULPS behavior

* Feature Enhancement: Dynamic IDELAY TAP value setting in Fixed Calibration mode of 7 Series MIPI D-PHY RX configuration

* Feature Enhancement: Resetting the Bit-Slice FIFO for LP to HS Mode Transition

* Other: Added support for additional 7 Series devices

MIPI DSI Tx Controller (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores

MIPI DSI Tx Subsystem (2.0)

* Version 2.0 (Rev. 2)

* General: Revision Change in subcores

* Revision change in one or more subcores

Mailbox (2.1)

* Version 2.1 (Rev. 9)

* Feature Enhancement: Added support for implementing FIFO with Ultra RAM

Memory Helper Core (1.4)

* Version 1.4

* No changes

 

Memory Interface Generator (MIG 7 Series) (4.1)

* Version 4.1

* General: Vivado 2018.1 software support.

MicroBlaze (10.0)

* Version 10.0 (Rev. 6)

* General: Add waivers to suppress reported invalid DRC and CDC violations

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 13)

* General: Add waivers to suppress reported invalid CDC violations

MicroBlaze MCS (3.0)

* Version 3.0 (Rev. 8)

* Revision change in one or more subcores

Multiplier (12.0)

* Version 12.0 (Rev. 14)

* Revision change in one or more subcores

Multiply Adder (3.0)

* Version 3.0 (Rev. 12)

* Revision change in one or more subcores

Mutex (2.1)

* Version 2.1 (Rev. 8)

* No changes

PCIe PHY IP (1.0)

* Version 1.0 (Rev. 8)

* General: Enabled Gen4 speed for -2L speedgrade UltraScale+ devices

* General: Updated bit width of "rst_psrst_n_r" signal in UltraScale+ variant of phy_wrapper module

* Revision change in one or more subcores

PR AXI Shutdown Manager (1.0)

* Version 1.0

* General: Initial release

PR Bitstream Monitor (1.0)

* Version 1.0

* General: Initial release

Partial Reconfiguration Controller (1.3)

* Version 1.3

* New Feature: Added support bitstream debug identifiers in compressed bitstreams

* New Feature: Changed timing of rm_shutdown_req signal

* Revision change in one or more subcores

Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 5)

* No changes

Peak Cancellation Crest Factor Reduction (6.1)

* Version 6.1 (Rev. 3)

* Feature Enhancement: PC-CFR register read back big fix (RADIP-553).

* Revision change in one or more subcores

Polar Encoder/Decoder (1.0)

* Version 1.0

* General: Initial release

Processor System Reset (5.0)

* Version 5.0 (Rev. 12)

* No changes

QDRII+ SRAM (MIG) (1.4)

* Version 1.4 (Rev. 4)

* General: Updated for 2018.1

* Revision change in one or more subcores

QDRIV SRAM (MIG) (2.0)

* Version 2.0 (Rev. 4)

* General: Updated for 2018.1

* Revision change in one or more subcores

 

QDRIV SRAM PHY IP (2.0)

* Version 1.2

* No changes

 

QSGMII (3.4)

* Version 3.4 (Rev. 3)

* General: Added support for Automotive Artix 7a12t and 7a25t devices

* Revision change in one or more subcores

Queue DMA Subsystem for PCI Express (PCIe) (1.0)

* Version 1.0

* General: Initial release

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 12)

* Revision change in one or more subcores

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 12)

* No changes

RLDRAM3 (MIG) (1.4)

* Version 1.4 (Rev. 4)

* General: Updated for 2018.1

* Revision change in one or more subcores

RXAUI (4.4)

* Version 4.4 (Rev. 3)

* General: Added support for xa7a12t and xa7a25t devices

* Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 14)

* Revision change in one or more subcores

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 13)

* Revision change in one or more subcores

Reset Verification IP (1.0)

* Version 1.0 (Rev. 1)

* General: production release

SC EXIT (1.0)

* Version 1.0 (Rev. 6)

* No changes

SC MMU (1.0)

* Version 1.0 (Rev. 5)

* No changes

SC SI_CONVERTER (1.0)

* Version 1.0 (Rev. 5)

* No changes

SC SPLITTER (1.0)

* Version 1.0 (Rev. 2)

* No changes

SC TRANSACTION_REGULATOR (1.0)

* Version 1.0 (Rev. 6)

* No changes

SDI RX to Video Bridge (2.0)

* Version 2.0

* No changes

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 8)

* No changes

SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 5)

* No changes

 

SMPTE UHD-SDI RX (1.0)

* Version 1.0

* No changes

 

SMPTE UHD-SDI RX SUBSYSTEM (2.0)

* Version 2.0

* Bug Fix: Updated XDC constraints in ZCU106 UHD-SDI Pass-Through example Design

* Bug Fix: Fixed ST352 valid output to assert for 4 frames continuously

* Bug Fix: Updated VID_LOCK interrupt to include ST352 valid when it is mandatory for given SDI standard

* New Feature: Added Native SDI and Native Video interface support

* New Feature: Added ZCU106 UHD-SDI RX-Only Example Design support

* New Feature: Added KCU116 UHD-SDI Audio-Video Loopback Example Design support

* New Feature: Added ZCU106 UHD-SDI Audio-Video Pass-Through Example Design support

* New Feature: Resource optimization for 3-G SDI mode

* Revision change in one or more subcores

 

SMPTE UHD-SDI TX (1.0)

* Version 1.0

* No changes

 

SMPTE UHD-SDI TX SUBSYSTEM (2.0)

* Version 2.0

* New Feature: Added Native SDI and Native Video interface support

* New Feature: Added YUV420 support and can be controlled through MODULE_CTRL register

* New Feature: Resource optimization for 3-G SDI mode

* Revision change in one or more subcores

 

SPDIF/AES3 (2.0)

* Version 2.0 (Rev. 19)

* Bug Fix: Fixed Channel Status Bits for Channel 0

* Feature Enhancement: A new interrupt has been added in SPDIF RX to indicate a change in Channel Status data

* Feature Enhancement: All the registers bits for Channel user data, Channel Status data have been updated to report value in "31 downto 0" format

* Other: IP updated to use XPM FIFO

* Other: RX configuration provides a reference Fs output

* Other: IP files are now delivered as encrypted sources. There is no need for a license.

* Revision change in one or more subcores

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 11)

* Bug Fix: Added an input buffer for tristate_output input port

 

Sensor Demosaic (1.0)

* Version 1.0 (Rev. 2)

* New Feature: Option to use UltraRAM for Line Buffers in UltraScale+ devices

* Other: Supported devices and production status are determined automatically, to simplify support for future devices

* Other: Updated synthesizable example design

* Revision change in one or more subcores

Serial RapidIO Gen2 (4.1)

* Version 4.1 (Rev. 3)

* General: Change in warning enablement in Block Design

* Revision change in one or more subcores

SmartConnect AXI2SC Bridge (1.0)

* Version 1.0 (Rev. 5)

* No changes

SmartConnect Node (1.0)

* Version 1.0 (Rev. 8)

* Bug Fix: Add FIFO output register parameter for direct control.

* Bug Fix: Add async mode for fifo_size 0 using xpm_cdc_handshake for minimum area mode.

SmartConnect SC2AXI Bridge (1.0)

* Version 1.0 (Rev. 5)

* No changes

SmartConnect Switchboard (1.0)

* Version 1.0 (Rev. 4)

* No changes

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 11)

* General: Add support for new devices XA7S6, XA7S15, XA7S25, XA7S75, XA7S100

* General: Supported devices' production status are now determined automatically.

Soft-Decision FEC (1.1)

* Version 1.1

* General: Initial release

Switch Core Top (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores

System Cache (4.0)

* Version 4.0 (Rev. 4)

* Bug Fix: Corrected XPM memory write strobe generation

* Other: Added checks to prevent configurations with invalid master address space size

System ILA (1.1)

* Version 1.1 (Rev. 2)

* General: Configured System ILA to disable mark debug in AXI protocol checker

* Revision change in one or more subcores

 

System Management Wizard (1.3)

* Version 1.3 (Rev. 7)

* General: Corrected Alarm level calculations.

* General: Updated Master SYSMON placement for VU11p devices.

* General: TEMPERATURE channel is always enabled when USE_TEMP_BUS is used.

* General: Corrected External channel Vaux supply range, depending on the pins available in the device.

 

TMR Comparator (1.0)

* Version 1.0 (Rev. 1)

* No changes

TMR Inject (1.0)

* Version 1.0 (Rev. 2)

* Feature Enhancement: Respond to all LMB accesses, read returns zero and write to undefined register ignored

TMR Manager (1.0)

* Version 1.0 (Rev. 3)

* General: Updated example design script to support JSON Block Design format

TMR Soft Error Mitigation Interface (1.0)

* Version 1.0 (Rev. 4)

* Bug Fix: Ensure that clock frequency is propagated to RTL for UART baud rate calculation

* Revision change in one or more subcores

TMR Voter (1.0)

* Version 1.0 (Rev. 1)

* No changes

TSN Endpoint Block (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

TSN Tri Mode Ethernet MAC (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

Time-Aware DMA (1.0)

* Version 1.0

* First Public Release of IP

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 4)

* No changes

Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 11)

* Bug Fix: Fix corner case RX Stats bug - Undersize counter does not increment when an properly formed 63-byte frame is received with carrier extend present

* Bug Fix: For UltraScale/UltraScale+ device, attribute REFCLK_FREQUENCY on I/O delay elements is corrected to indicate the frequency of reference clock used

* Bug Fix: Updated Example Design XDC constraints for cases in which XST is renaming FSM state variable names

* Feature Enhancement: Packet buffers moved to XPM - No functional changes

* Revision change in one or more subcores

UHD-SDI AUDIO (1.0)

* Version 1.0

* New Feature: Initial release

* New Feature: AXI4-Lite & Non-AXI4 (Generic ports) based configuration interface

* New Feature: AXI-Stream interface carrying audio samples in AES format

* New Feature: Embeds & Extracts up to 16-Channels of Audio

* New Feature: Supports multiple sample rates (32 KHz, 44.1 KHz and 48 KHz)

* New Feature: Supports SMPTE272M for SD-SDI

* New Feature: Supports SMPTE299M-1 for HD/3G SDI

* New Feature: Enhanced SMPTE299M-1 to transfer data in 6G & 12G modes

 

UHD-SDI GT (1.0)

* Version 1.0 (Rev. 1)

* Bug Fix: Improved reset structure DRP state machine

* New Feature: Added UltraScale Plus GTY Transceiver support

* New Feature: Added Data Flow configuration with Duplex and RX-Only options

* New Feature: Added Multi-link support

* New Feature: Added SharedLogic for GT COMMON block

UHD-SDI Video Pattern Generator (1.0)

* Version 1.0

* Initial release

 

UltraScale 100G Ethernet Subsystem (2.3)

* Version 2.3 (Rev. 2)

* Port Change: Added gt_txpippmen and gt_txpippmsel input ports to the GT if Enable Additional GT Control/Status and DRP Ports is selected

* Feature Enhancement: Added .h header file for AXI4 Lite register information

* Other: Moved the address space for ANLT STAT registers from 0x0758-0x0778 to 0x0258-0x0278. STAT_AN_STATUS, STAT_AN_ABILITY and STAT_AN_LINK_CTL registers are re-named to STAT_AN_STATUS_REG, STAT_AN_ABILITY_REG and STAT_AN_LINK_CTL_REG.

* Other: Re-named few AXI4 registers in the register map. Please refer to the .h header file or (PG165).

* Revision change in one or more subcores

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)

* Version 4.4 (Rev. 2)

* Feature Enhancement: Modified the Tandem Stage1 np_req credit allocation. Tandem stage1 will now allocate one np_req credit rather than infinite np_req credits. This allows better control of credit allocation after stage2 is loaded.

* Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.7)

* Version 1.7 (Rev. 3)

* Feature Enhancement: Added new transceiver configuration preset options for GTY-12G_SDI/GTH-12G_SDI

* Feature Enhancement: Updated the choice of GTYE4 Reference clock sharing for line rates between 16.375 and 28.21 Gb/s

* Other: Updated to use simulation only bypass logic under pragma control by default for CPLL calibration module for UltraScale+ devices

* Other: Fixed a bug in the customization GUI that prevented Fractional-N calculator feature for some configurations

* Other: Adjusted the customization GUI for comma alignment selection to match the UltraScale+ FPGAs Data Sheet

* Other: Adjusted line rate and associated frequency limits for 8B/10B encoding configurations to match the UltraScale+ FPGAs Data Sheet

* Revision change in one or more subcores

UltraScale Soft Error Mitigation (3.1)

* Version 3.1 (Rev. 7)

* Bug Fix: Resolve (Xilinx Answer 70487) where SEM controller targeting KU085 will not boot up

* Bug Fix: Corrected the bit width for the fetch_rxdata input tie-off in the top level example design file

UltraScale+ 100G Ethernet Subsystem (2.4)

* Version 2.4 (Rev. 2)

* Port Change: Added gt_txpippmen and gt_txpippmsel input ports to the GT if Enable Additional GT Control/Status and DRP Ports is selected

* Feature Enhancement: Added .h header file for AXI4 Lite register information

* Other: Updated the CMACE4 core location when RSFEC Transcode Bypass option is selected

* Other: Moved the address space for ANLT STAT registers from 0x0758-0x0778 to 0x0258-0x0278. STAT_AN_STATUS, STAT_AN_ABILITY and STAT_AN_LINK_CTL registers are re-named to STAT_AN_STATUS_REG, STAT_AN_ABILITY_REG and STAT_AN_LINK_CTL_REG.

* Other: Re-named few AXI4 registers in the register map. Please refer .h header file or (PG203).

* Revision change in one or more subcores

UltraScale+ PCI Express 4c Integrated Block (1.0)

* Version 1.0 (Rev. 2)

* Feature Enhancement: Added tandem support for the xcvu37p device.

* Other: Added Core Interface Parameters GUI page.

* Other: Added ATS/PRI support for Endpoint mode in the GUI.

* Revision change in one or more subcores

UltraScale+ PCI Express Integrated Block (1.3)

* Version 1.3 (Rev. 2)

* Feature Enhancement: Modified the Tandem Stage1 np_req credit allocation. Tandem stage1 will now allocate one np_req credit rather than infinite np_req credits. This allows better control of credit allocation after stage2 is loaded.

* Feature Enhancement: Added GEN4 control skip filter module with parameter(ctrl_skip_mask).This can be used for EndPoint to work with GEN4 RootPort generating control skips.

* Feature Enhancement: Added an option to set the MCAP bitstream version register within the MCAP register space.

* Feature Enhancement: Added Core Interface Parameters GUI page.

* Feature Enhancement: Added support for fsve1156,fsvg1517 packages for xczu25dr,xczu27dr,xczu28dr devices and fsvf1760 for xczu29dr device

* Revision change in one or more subcores

Universal Serial XGMII Ethernet Subsystem (1.0)

* Version 1.0 (Rev. 2)

* General: Virtex UltraScale Plus parts moved to production status

* General: Updated Example design Packet Generator Checker module when AXI4-Lite Interface is enabled - Added logic to prevent optimization of the AXI4-Lite read interface logic post implementation.

* Revision change in one or more subcores

Utility Reduced Logic (2.0)

* Version 2.0 (Rev. 4)

* Validating the minimum value of C_SIZE to be > 0 and added GUI tool tip when the validation failed

 

Utility Vector Logic (2.0)

* Version 2.0 (Rev. 1)

* No changes

 

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 18)

* General: Internal subcore reference changes

 

Video AXI4S Remapper (1.0)

* Version 1.0 (Rev. 8)

* Revision change in one or more subcores

Video Color Space Conversion and Correction (1.0)

* Version 1.0 (Rev. 10)

* New Feature: Option to use UltraRAM for Line Buffers in UltraScale+ devices

* Other: Updated synthesizable example design

* Revision change in one or more subcores

Video Deinterlacer (5.0)

* Version 5.0 (Rev. 10)

* Feature Enhancement: Added 64-bit address for memory mapped AXI4 interface

* Revision change in one or more subcores

Video DisplayPort 1.4 RX Subsystem (1.0)

* Version 1.0

* Initial Release

* Support for Single stream transport (SST)

* DisplayPort RX Subsystem with 1/2/4 lanes

* Dynamic link rate support (1.62/2.7/5.4/8.1 Gbps)

* Dynamic support of 6, 8, 10, 12, or 16 bits per component (BPC)

* Dynamic support of RGB/YCbCr444/YCbCr422 color formats

* Supports SDP packet for static HDR mode

* AXI4 Stream video output interface

* Native video output interface

* External 16-bit Video PHY interface

* Optional AXI4 Stream audio output interface

* AXI IIC Controller support to program retimer

Video DisplayPort 1.4 TX Subsystem (1.0)

* Version 1.0

* Initial Release

* Support for Single stream support (SST)

* DisplayPort TX Subsystem with 1/2/4 lanes

* Dynamic link rate support (1.62/2.7/5.4/8.1 Gbps)

* Dynamic support of 6, 8, 10, 12, or 16 bits per component (BPC)

* Dynamic support of RGB/YCbCr444/YCbCr422 color formats

* Supports SDP packet for static HDR mode

* AXI4 Stream video input interface

* Native video input interface

* External 16-bit Video PHY interface

* Optional AXI4 Stream audio input interface

Video Frame Buffer Read (2.0)

* Version 2.0 (Rev. 2)

* New Feature: Added support for interlaced video

* New Feature: Added ability to flush pending AXI transactions before reset

* Feature Enhancement: Added BGR8 memory format

* Other: Updated example design

* Revision change in one or more subcores

Video Frame Buffer Write (2.0)

* Version 2.0 (Rev. 2)

* New Feature: Added support for interlaced video

* New Feature: Added ability to flush pending AXI transactions before reset

* Feature Enhancement: The AXI MM interface is operating in conservative mode

* Feature Enhancement: Added BGR8 memory format

* Other: Updated example design

* Revision change in one or more subcores

Video Horizontal Chroma Resampler (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores

Video Horizontal Scaler (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores

Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 8)

* Bug Fix: Updated YUV420 remapper to recover from early/late EOL or SOF

Video Letterbox Engine (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores

Video Mixer (3.0)

* Version 3.0

* New Feature: Option to use UltraRAM for Line Buffers in UltraScale+ devices

* Feature Enhancement: Increased number of overlay layers to 8

* Feature Enhancement: Added BGR8 memory format

* Other: Updated synthesizable example design

* Revision change in one or more subcores

Video On Screen Display (6.0)

* Version 6.0 (Rev. 15)

* No changes

Video PHY Controller (2.2)

* Version 2.2

* Bug Fix: Fixed case where TMDS clock control was sometimes not connected to the control register 0x138/0x158

* Bug Fix: Fixed case where GUI generates incorrect interface for some PLL/REFCLK selection in RX

* Bug Fix: Fixed Critical Warning when generating IPI OOC run

* Bug Fix: Fixed REFCLK selection register not working when neither TX or RX REFCLK uses GTREFCLK0 or GTREFCLK1 as source

* Feature Enhancement: HDMI protocol support added for GTYE4

* Feature Enhancement: Added 2 byte support for HDMI

* Feature Enhancement: Added GT channel support for TMDS clock in HDMI

* Feature Enhancement: Mapped TXDIFFCTRL to register 0x7C

* Feature Enhancement: Added TXPI_Port_EN userparameter for GTHE3, GTHE4 & GTYE4 devices to optionally enable TXPI ports

* Other: Removed DP protocol support for GTPE2

* Revision change in one or more subcores

Video Processing Subsystem (2.0)

* Version 2.0 (Rev. 8)

* New Feature: Option to use UltraRAM for Line Buffers in UltraScale+ devices

* Other: Updated synthesizable example design

* Revision change in one or more subcores

Video Test Pattern Generator (7.0)

* Version 7.0 (Rev. 10)

* General: Updated synthesizable example design

* General: Changed baud rate in example design from 9600 to 115200

* Revision change in one or more subcores

Video Timing Controller (6.1)

* Version 6.1 (Rev. 12)

* No changes

Video Vertical Chroma Resampler (1.0)

* Version 1.0 (Rev. 10)

* Revision change in one or more subcores

Video Vertical Scaler (1.0)

* Version 1.0 (Rev. 10)

* New Feature: Option to use UltraRAM for Line Buffers in UltraScale+ devices

* Other: Updated synthesizable example design

* Revision change in one or more subcores

Video to SDI TX Bridge (2.0)

* Version 2.0

* No changes

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)

* Version 4.3 (Rev. 2)

* Bug Fix: Fixed timing issues in Tandem mode for XC7VX690T device by adding DSP and Block Rams, in the floorplan, in the constraints file

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 9)

* Revision change in one or more subcores

XADC Wizard (3.3)

* Version 3.3 (Rev. 5)

* No changes

 

XAUI (12.3)

* Version 12.3 (Rev. 3)

* General: Removed support for devices that have less than 4 GTs

* Revision change in one or more subcores

XHMC (1.0)

* Version 1.0 (Rev. 6)

* Bug Fix: Correction axi-lite rvalid bug

* Revision change in one or more subcores

 

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 12)

* No changes

ZYNQ UltraScale+ VCU (1.1)

* Version 1.1

* Port Change: NONE

* Bug Fix: Fixed parameters to address XPE Power Analysis for the VCU Decoder

* Bug Fix: Updated GUI to include units for Encoder Buffer Size

* Feature Enhancement: New core parameters to handle the multi-stream use case

* Other: Fixed change log issues

 

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 6)

* No changes

 

ZYNQ7 Processing System VIP (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores

ZYNQMPSOC Processing System VIP (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

Zynq UltraScale+ MPSoC (3.2)

* Version 3.2

* Bug Fix: 1.emio_enet0_enet_tsu_timer_cnt port is enabled.

* Bug Fix: 2.RFSoC Devices were using incorrect Si revision.

* Bug Fix: 3.IP now allows Live video pins enabling without Display port using at-least one GT.

* Bug Fix: 4.Updated the ddrc, phy driver files to prevent overflow/underflow issues.

* Bug Fix: 5.Changed LPDDR3 cfg.speed_bin to cfg.freq_mhz for EMR2-RL/WL calculation.

* Bug Fix: 6.Fixed the tphy_wrcslat parameter.

* Bug Fix: 7.Added separate parameters for USB3 HUB port enablement. PSU__USE__USB3_0_HUB and PSU__USE__USB3_1_HUB.

* Bug Fix: 8.Fixed incorrect AMS clock setting in psu_init.

* Bug Fix: 9.Simplified PCW-GEM TSU CLK selection by setting bit[22] of GEM_CLK_CTRL when TSU clock loop backed from PL and exposing emio_enet0_enet_tsu_timer_cnt[93:0] output port even when TSU clock is source from PS.

* Bug Fix: 10.Cache Coherency feature is tested for EL1 - NS (on Native Linux) and EL3 applications.

* Feature Enhancement: 1 - The fractional clocking enable (FracEn) option is provided in Vivado for the ACPU to facilitate their precise

* Feature Enhancement: clocking. When this option is checked/enabled the fractional value for the feedback value is configured for the respective PLL.

* Feature Enhancement: 2 - Self Refresh Functionality - When feature is enabled then top 1 MB of Lower DDR is reserved for internal purposes.

* Feature Enhancement: 3 - MPSoC PMU GPO initial state polarity configuration is supported from 2018.1.

* Feature Enhancement: 4 - When the DDR preset is selected, the clocking solution will be adjusted to use DPLL for DDR and DPLL will be given high priority/biased to achieve the DDR Memory Interface Device Frequency.

* Feature Enhancement: 5 - Zynq UltraScale+ RFSOC based new devices are added

* Revision change in one or more subcores

Zynq UltraScale+ RF Data Converter (2.0)

* Version 2.0

* Port Change: Removed user_sysref port and replaced with optional dac_user_sysref and adc_user_sysref ports. See product guide for more information

* Port Change: Added ADC over voltage and over range to the real time signal ports

* Port Change: Re-named ADC real time signal and calibration freeze ports

* Port Change: Changed Calibration Freeze Port interface to per tile. No change to actual ports

* Port Change: Removed bit 15 from ADC and DAC cmn_control debug ports

* Bug Fix: Fixed issue with ADC CONTROL_COMMON inputs being tied all to same input

* Bug Fix: Fixed synthesis issue when ADC calibration mode is set to mode1, data output is I/Q and mixer is bypassed

* Bug Fix: Fixed issue with ADC/DAC tile debug ports (pll_dmon, pll_lock, status and done) not being driven

* Bug Fix: Always enable the DAC Vdda bleeder

* New Feature: Added support for Multi Tile SYNC

* New Feature: Added GUI option to enable/disable dither

* New Feature: Added GUI option to speed-up Calibration Time

* New Feature: Added GUI option for Auto Calibration Freeze

* New Feature: Added GUI option for Simple Converter Set-up

* New Feature: Added support for creating example design in IP Integrator

* Feature Enhancement: Updated ADC calibration freeze settings

* Feature Enhancement: Enhanced Vco settings

* Feature Enhancement: Freeze calibration when over-voltage or over-range converter outputs are asserted

* Feature Enhancement: Cleared datapath, fabric and decoder interrupts after start-up

* Feature Enhancement: Reset the ADC NCO phase to align I and Q output on 4GSPS ADCs

* Feature Enhancement: Increased Max Sampling Rates for ADC and DAC.

* Feature Enhancement: Optimized calibration process to shorten start up time

* Feature Enhancement: Added support for NCO frequencies above Fs/2

* Feature Enhancement: Improved GUI layout

* Other: Removed GUI option to select external/internal SYSREF

* Other: Release AXI IPIF files into same directory as the other HDL

audio_tpg_v1_0 (1.0)

* Version 1.0

* Initial release

axi_msg (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

axi_sg (4.1)

* Version 4.1 (Rev. 9)

* Revision change in one or more subcores

interrupt_controller (3.1)

* Version 3.1 (Rev. 4)

* No changes

lib_bmg (1.0)

* Version 1.0 (Rev. 10)

* No changes

lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_fifo (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores

lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes

 

AR# 70699
Date 05/30/2018
Status Active
Type Release Notes
Tools
  • Vivado Design Suite
Page Bookmarked