The AXI4-Stream pixel mapping implementation of the DisplayPort RX/TX Subsystems differs from the Video over AXI4-Stream pixel mapping definition in (UG934) for YUV422 and Y-only.
How can I connect the DisplayPort RX/TX Subsystems to other Xilinx Video IPs which do align with the Video over AXI4-Stream pixel mapping definition in (UG934)?
This is a known limitation of the DisplayPort TX/RX Subsystem.
Future versions of the DisplayPort 1.4 RX/TX Subsystems will have an updated AXI4-Interface pixel mapping that aligns with the Video over AXI4-Stream pixel mapping in (UG934).
The DisplayPort (1.2) RX/TX Subsystems require the user to do a bridge for the data.
For new designs, we recommend the use of the DisplayPort 1.4 RX/TX Subsystems.