AR# 70715

DisplayPort TX/RX Subsystem - Why do I see a difference in the Subsystem AXI4-Interface pixel packing and the Video over AXI4-Interface pixel mapping definition in UG934?

Description

The AXI4-Stream pixel mapping implementation of the DisplayPort RX/TX Subsystems differs from the Video over AXI4-Stream pixel mapping definition in (UG934) for YUV422 and Y-only.

How can I connect the DisplayPort RX/TX Subsystems to other Xilinx Video IPs which do align with the Video over AXI4-Stream pixel mapping definition in (UG934)?

Solution

This is a known limitation of the DisplayPort TX/RX Subsystem.

Future versions of the DisplayPort 1.4 RX/TX Subsystems will have an updated AXI4-Interface pixel mapping that aligns with the Video over AXI4-Stream pixel mapping in (UG934).

The DisplayPort (1.2) RX/TX Subsystems require the user to do a bridge for the data. 

For new designs, we recommend the use of the DisplayPort 1.4 RX/TX Subsystems.

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AR# 70715
Date 05/04/2018
Status Active
Type General Article
IP