UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 70715

DisplayPort TX/RX Subsystem - Why do I see a difference in the Subsystem AXI4-Interface pixel packing and the Video over AXI4-Interface pixel mapping definition in UG934?

Description

The AXI4-Stream pixel mapping implementation of the DisplayPort RX/TX Subsystems differs from the Video over AXI4-Stream pixel mapping definition in (UG934) for YUV422 and Y-only.

How can I connect the DisplayPort RX/TX Subsystems to other Xilinx Video IPs which do align with the Video over AXI4-Stream pixel mapping definition in (UG934)?

Solution

This is a known limitation of the DisplayPort TX/RX Subsystem.

Future versions of the DisplayPort 1.4 RX/TX Subsystems will have an updated AXI4-Interface pixel mapping that aligns with the Video over AXI4-Stream pixel mapping in (UG934).

The DisplayPort (1.2) RX/TX Subsystems require the user to do a bridge for the data. 

For new designs, we recommend the use of the DisplayPort 1.4 RX/TX Subsystems.

Linked Answer Records

Master Answer Records

AR# 70715
Date 05/04/2018
Status Active
Type General Article
IP
Page Bookmarked