I have a packaged user IP that consist of two or more different Xilinx IPs.
Based on the VHDL if-generate statement, some of the Xilinx IP are not included in the hierarchy and will not be used for the synthesis and later flows.
My top level project has a block design (BD) that instantiates my user IP and the output products are generated as "Out of Context Per IP".
A "dont_touch.xdc" file is generated in the C:/[directory]/[project].runs/[ip_name]/ path which uses "set_property DONT_TOUCH TRUE" for both IPs.
While synthesizing the design, Vivado is picking up the "set_property" commands for the Xilinx IP cores that are not being used, and is issuing a critical warning similar to the following:
The error is issued because the constraints for the unused IP core are processed even though this IP core is not being used.
To work around this issue, use the Manual Compile Order setting for hierarchy update when packaging the user IP.
This issue will be fixed in Vivado 2018.3.