This answer record serves as the Vivado SDAccel 2017.4 Release Notes, and contains Links to information about what is included in the update.
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SDAccel Development Environment Changes for 2017.4
SDAccel Known issues:
|(Xilinx Answer 70450)||2017.4 - SDAccel - Frequency Scaling of Kernel Clock not applied|
|2017.4 - SDAccel - OpenCL support of LLVM 3.9|
|2017.4 - SDAccel - xocc options for dynamic platform (5.0 DSA) have changed|
|2017.4 - SDAccel - design fails with "ERROR: [KernelCheck 83-114] Kernel 'black_scholes' port 'M_AXI_GMEM' is not mapped from any kernel argument. There must be at least one kernel argument that maps onto every AXI4 master port on the kernel IP"|
|(Xilinx Answer 70933)||2017.4 - SDAccel - Motherboard and System Recommendations|
|2017.4 - SDAccel - Design fail with interconnect_ddr4_mem00_0.dcp is not a valid design checkpoint|
|2017.4 - SDAccel - Moving vcu1525_dyanmic_5_0 from one host to another corrupted golden image|
|(Xilinx Answer 70936)||2017.4 - SDAccel - Cold Boot required after upgrading/downgrading DSA using XBSAK flash|
|2017.4 - SDAccel - AWS failures terminate called after throwing an instance of 'xrt::error' with 7v3 and ku3-2ddr-xpr|
|2017.4 - SDAccel - Bandwidth mismatch between VCU1525 and KCU1500 dynamic DSAs for the same testcase|
|2017.4 - SDAccel - RTL Kernels|