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AR# 7084

V1.5 CORE Generatior - Delay Element locks up and only provides 2 clock delays.


Keywords: lock, delay, CORE Generator, COREGen

Urgency: Standard

General Description:
Under certain conditions, the CORE Generator Delay Element may delay
for 2 clock cycles less than the user-specified number of cycles.


The Delay Element delivered during the CORE Generator 1.5 timeframe
consists of a registered RAM module and an LFSR counter,
which generates the addresses for the RAM.

The LFSR in this core may occasionally initialize to an illegal state
of "11" after the GSR is released. The problem appears to be associated
with excessive skew (~15ns or more) in the GSR net delays between
the device's flip-flops in the presence of a free-running clock.
This means that typically, only some of the Delay Elements in a user's
design will experience the problem.

(In one instance, the GSR to clock delay was about 30ns
on the device, compared to the 13ns delay of the free-running
75 MHz clock clocking the circuit.)

The LFSR is not able to recover from the "11"
state because the next state for "11" is not defined in the
logic. As a result, only 2 clock cycle delays ended up being added
by the Delay Element--one by the RAM, and the other
by the RAM's output register.

This problem has been fixed in the version of the Delay Element
delivered with the 2.1i version of CORE Generator.

In addition, several other work-arounds are possible:

1. Assert GSR synchronously after the chip comes out of
configuration. (This does not require modification of the
module, but it will only work on systems with clocks slower than
approximately 10 MHz.)

2. Add circuitry to the EDIF to reset the LFSR whenever
it reaches the "11" state. (This is somewhat difficult
to do.)

3. In the case of a 4-cycle Delay Element, the XNOR gate, which is
sourced by the two flip-flops, can be replaced by a NOR gate; do this by
editing the EDIF netlist for that element.

4. Instead of using the Delay Element, connect a down
counter to a registered RAM with logic to detect (Terminal Count-1).

5. Instead of using the Delay Element, use a Shift Register.
(However, this is a less efficient use of resources.)
AR# 7084
Date 02/15/2001
Status Archive
Type ??????
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