If you have a design that uses the PL IIC interface on a ZCU106 board, you might see the below error during the place design stage:
The Drive Strength of the PL IIC pins is not set in board files.
The error is seen only in the 2018.1 release. The tool incorrectly allowed default setting in 2017.4 and prior releases.
We see the issue only for the ZCU106 board, because the IIC interface is located in the HP bank and uses the LVCMOS12 IO-Standard.
No other Evaluation board has this typical placement and drive strength combination.
As per the table below (snippet from UG571), drive strength which defaults to 12 is outside of the permissible values for LVCMOS12 on HP bank:
In order to avoid the error, you can add a top level constraint for IIC pins with appropriate drive strength.