AR# 70907


2018.1 Vivado Constraints - [DRC BIVB-1] Bank I/O standard Support: Bank 65 has incompatible IO ...


If you have a design that uses the PL IIC interface on a ZCU106 board, you might see the below error during the place design stage:

[DRC BIVB-1] Bank IO standard Support: Bank 65 has incompatible IO(s) because:
The LVCMOS12 I/O standard does not support a drive strength of 12.
Move the following ports or change their properties: iic0_pl_scl_io, iic0_pl_sda_io, iic1_pl_scl_io and iic1_pl_sda_io


The Drive Strength of the PL IIC pins is not set in board files. 

The error is seen only in the 2018.1 release. The tool incorrectly allowed default setting in 2017.4 and prior releases.

We see the issue only for the ZCU106 board, because the IIC interface is located in the HP bank and uses the LVCMOS12 IO-Standard.

No other Evaluation board has this typical placement and drive strength combination. 

As per the table below (snippet from UG571), drive strength which defaults to 12 is outside of the permissible values for LVCMOS12 on HP bank:


In order to avoid the error, you can add a top level constraint for IIC pins with appropriate drive strength.

For example:

   set_property DRIVE 8 [get_ports iic0_pl_scl_io]
   set_property DRIVE 8 [get_ports iic0_pl_sda_io]

AR# 70907
Date 04/10/2018
Status Active
Type General Article
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