AR# 70941

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25G/50G/100G and Flex-O Reed-Solomon Forward Error Correction (RS-FEC) cores - 2018.1 and earlier - Example Design alignment markers incorrect when generated on Windows

Description

In Vivado 2018.1 and earlier versions, when generating the 25G, 50G, 100G or Flex-O RS-FEC cores on a Windows machine, the RX and TX alignment markers in the RS-FEC example design are incorrect.

The upper 32-bits of each alignment marker is incorrectly tied to 0 in the core_name_exdes.v file.

For example, for 100G:

 

    .CTL_RX_VL_MARKER_ID0      (64'h000000003E97DE00),
    .CTL_RX_VL_MARKER_ID1      (64'h00000000628E7100),
     ...
    .CTL_RX_VL_MARKER_ID18     (64'h00000000A099D500),
    .CTL_RX_VL_MARKER_ID19     (64'h000000003F0F1A00),

    .CTL_TX_VL_MARKER_ID0      (64'h000000003E97DE00),
    .CTL_TX_VL_MARKER_ID1      (64'h00000000628E7100),
     ...
    .CTL_TX_VL_MARKER_ID18     (64'h00000000A099D500),
    .CTL_TX_VL_MARKER_ID19     (64'h000000003F0F1A00),

Solution

To work around this issue, the example design can be generated on a Linux machine or the RX and TX alignment marker values can be updated manually in the core_name_exdes.v file.

This issue only applies to the stand-alone RS-FEC core example design and does not affect the RS-FEC core itself or any cores such as the 25G/50G/100G Ethernet Subsystems that use the RS-FEC as a subcore.

This issue is scheduled to be fixed in Vivado 2018.2.

AR# 70941
Date 04/16/2018
Status Active
Type General Article
IP
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