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  3. AR# 70994: LogiCORE UHD-SDI GT - Why does the UHD-SDI GT wrapper fail to implement when selecting a multi-link configuration?

AR# 70994

LogiCORE UHD-SDI GT - Why does the UHD-SDI GT wrapper fail to implement when selecting a multi-link configuration?

Description

Why does the UHD-SDI GT wrapper fail to implement when selecting a multi-link configuration?

When instantiating a UHD-SDI _GT and selecting 2 for UHD-SDI GT Links, a second design_1_uhdsdi_gt_0_0_top instance is never instantiated.

This is shown in the screenshot below.





 


Solution

This is a known issue that occurs when a users tries to implement the multi-link configuration of the UHD-SDI GT Core.

This issue has been fixed in Vivado 2018.2 and later.

  • Vivado 2018.1 - Users can download the UHD-SDI GT patch from (Xilinx Answer 70974) to work around this issue.
  • Vivado 2018.2 - This issue is resolved in the UHD-SDI GT IP in Vivado 2018.2 and later.

Note: For an existing design, the output products of the IP need to be reset after applying the patch.

Xilinx recommends updating to the latest version of the IP.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
70291 LogiCORE UHD-SDI GT - Release Notes and Known Issues for the Vivado 2017.3 tool and later versions N/A N/A
70974 2018.1 LogiCORE UHD-SDI GT v1.0 - Patch Updates for the LogiCORE UHD-SDI GT v1.0 N/A N/A
68766 SMPTE UHD-SDI RX Subsystem - Release Notes and Known Issues for the Vivado 2017.3 tool and later versions N/A N/A
68767 SMPTE UHD-SDI Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2017.3 tool and later versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
71055 LogiCORE UHD-SDI GT v1.0 - Why do I get Critical Warnings and Errors mentioning a cmp_gt_sts pin when trying to implement the UHD-SDI GT? N/A N/A
AR# 70994
Date 07/03/2018
Status Active
Type General Article
Tools
IP