AR# 71015

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2018.1/2 Zynq UltraScale+ MPSoC: FSBL R5 application does not work with default isolation enabled.

Description

I have default isolation enabled in my design on a Zynq UltraScale+ MPSoC.

When the resulting HDF is exported to SDK to generate the FSBL and applications (for example hello world) on R5, the below processor combinations for running the FSBL and application do not work.

  1. FSBL running on R5, application running on R5
  2. FSBL running on A53, application running on R5

Solution

The R5 BSP needs an access for CRL_APB.

You will need to add an RPU subsystem or modify the code to route CRL_APB access to the PMUFW using xilpm.

Subsystem: RPU Master: RPU0 (Secure) Slave CRL_APB (Secure), RPU (Secure)

If you want to bypass the isolation configuration, set the value below in xfsbl_config.h:

#define FSBL_PROT_BYAPSS_EXCLUDE_VAL      (0U)

AR# 71015
Date 06/18/2018
Status Active
Type General Article
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