AR# 71019

|

Zynq UltraScale+ MPSoC: eMMC Booting Checklist

Description

This is a list of required items, necessary actions, and points to be considered, when debugging eMMC booting on Zynq UltraScale+ MPSoC.

Solution

Before opening a Service Request, collect all of the information requested below.

Note: (Xilinx Answer 65463) has the eMMC flashes tested by Xilinx on MPSoC. 

If the flash under test is NOT on that list be sure it is fully compliant with JEDEC specification version 4.51 (Standard Speed, High Speed and HS200).

1) Which eMMC Configuration is used?


In order to boot from eMMC the flash needs to be connected to the SDIO0controller over MIO[22:13] and the bank should be powered at 1.8V.

The software will run the eMMC at HS200 speed (200MHz), so if the bank is powered at 3.3V (max speed on the interface is "high speed" (50MHz)), the software will fail accessing the flash.

See (Xilinx Answer 69368) How to slow down eMMC from HS200 to High Speed (HS) in FSBL, u-boot and Linux

The Vivado Clock Configuration should have:


  • IOPLLat 1500MHz
  • SDIO0 at 200MHz

Any variations from this clock setup could cause issues.

See (UG1085) chapter 11 and 26.

Please provide the details of the eMMC configuration used and the board schematics.


2) Is Zynq Production Silicon?

Use XSCT to read:

  • The IDCODE from 0xFFCA0040
  • The PS_VERSION from 0xFFCA0044

Please provide the IDCODE and PS_VERSION.


3) Is the JTAG chain operating properly?


Use XSCT to try to connect to the CPU.

Please provide a JTAG chain description (how many devices on the chain, how many Zynq, Zynq in cascade or independent JTAG, any level shifter in the chain). Report any XSCT error.


4) In which phase of booting is Zynq failing? BootROM or FSBL?

In order to determine this, use an image with FSBL debug prints enabled. 

#define FSBL_DEBUG_DETAILED in xfsbl_debug.h

If some printing comes out on the UART during boot:

Please provide a log of the FSBL print out on the UART. FSBL is a user application and can be easily debugged using SDK.

Try to do a brief investigation before filing a Service Request.

  • If nothing comes out on the UART during boot, first double check the UART baudrate.

Please provide the status of INIT_B, PS_ERROR_OUT, CSU_BR_ERROR and BOOT_MODE_POR registers after the boot failure.


5) Is it working using u-boot and/or Linux?

Use the u-boot.elf or Linux pre-built from the latest released image on the wiki: http://www.wiki.xilinx.com/Zynq+Releases

mmc info, fatls, fatload, mount, etc ...

A debug option could be to limit the eMMC interface speed to "high" (50MHz) and see if the error persists. 

See (Xilinx Answer 69368) How to slow down eMMC from HS200 to High Speed (HS) in FSBL, u-boot and Linux

Note: (Xilinx Answer 69332) 2017.1 Zynq UltraScale+ MPSoC: U-boot needs a patch to run eMMC at HS200

Another option in u-boot is to use the following defines to collect more information on the test case:

  • DEBUG
  • CONFIG_MMC_TRACE

Please provide the log of the mmc commands to exercise the eMMC using the u-boot image built with the above defines. or the u-boot image from the wiki. Specify the u-boot version used.


6) Is the Xilinx stand-alone example working (xilffs)?

Some Debugging is required to understand where the example is failing (through the SDK debugger or by adding debug prints).

A debug option could be to limit the eMMC interface speed to "high" (50MHz) and see if the error persists.

See (Xilinx Answer 69368) How to slow down eMMC from HS200 to High Speed (HS) in FSBL, u-boot and Linux

Report the type of failure in the Xilinx stand-alone example


7) Suggested register dump:

These are a few registers the user should check to see if the clocking and TAP delay configuration is correct (See (UG1085) chapter 26):

  • ff18031c: sd_config_reg1
  • ff180320: sd_config_reg2
  • ff180324: sd_config_reg3
  • ff16002c: clkctrl_sdclkfreqsel
  • ff5e0104: dll_ref_ctrl
  • 0xFF16002C : reg_clockcontrol SDIO0
  • 0xFF180314: ITAP
  • 0xFF180318: OTAP

See http://www.wiki.xilinx.com/SD+controller for more details (also valid for eMMC).

AR# 71019
Date 06/01/2018
Status Active
Type General Article
Devices
People Also Viewed