Version Found: v4.0 (Rev1)
Version Resolved and other Known Issues: (Xilinx Answer 65443)
I am using the DMA / Bridge Subsystem for PCI Express in Bridge mode in an IP Integrator design.
Address Read and Write requests (AR/AW) on an AXIBAR, with a low and high address assigned in the upper 64-bit address range, return a decode error (DECERR).
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
The issue is due to the IP Integrator environment causing the IP to mismatch addresses from the Address Manager S_AXI_BAR address settings.
To work around this issue, use only addresses in the 32-bit addressing space for all AXI BARs associated with the DMA/Bridge Subsystem for PCI Express.
If an address in the 64-bit space is needed, revert to 2017.3 or upgrade to 2018.1. This issue is seen only in Vivado 2017.4.
06/03/2018 - Initial Release