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AR# 71097

Virtex UltraScale+ HBM - Example Design Simulation Issues with VCS, Questa Sim, or IES

Description

Version Found: HBM v1.0

Version Resolved: See (Xilinx Answer 69267)

Simulation errors can occur with the Example Design when using VCS, Questa Sim, or IES when using default settings.

Solution

To resolve simulation issues with VCS:


  • In the 2018.2 version, under the Simulation tab in the Vivado Project Settings add +notimingchecks to vcs.simulate.vcs.more_options
  • In the 2018.3 and 2019.1 versions, under the Simulation tab in the Vivado Project Settings add +notimingcheck to vcs.simulate.vcs.more_options

To resolve this issue for Questa Sim in Vivado 2018.2, 2018.3, or 2019.1:


  • Under the Compilation tab in the Vivado Project Settings add +notimingchecks to questa.compile.vlog.more_options
  • Under the Simulation tab in the Vivado Project Settings add -onfinish final +notimingchecks to questa.simulate.vsim.more_options

To resolve this issue for IES simulator in Vivado 2018.2, 2018.3, or 2019.1:

  • Under the Elaboration tab in the Vivado Project Settings add -notimingchecks to ies.elaboration.ncelab.more_options

If issues persist when using Vivado 2018.3 or 2019.1, see (Xilinx Answer 71795)


Revision History:

05/05/2018New Answer Record
05/21/2018Changed vlogan to vlog
12/10/2018Revised Description and added IES Simulator
01/07/2018Revised Title, Description, and Solution to be generic across all simulators and 2018.2 or 2018.3.  Added link to (Xilinx Answer 71795).
05/02/2019 Updated for 2019.1

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69267 Virtex UltraScale+ HBM Controller - Release Notes and Known Issues N/A N/A

Associated Answer Records

AR# 71097
Date 05/07/2019
Status Active
Type General Article
Devices
Tools
IP
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