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CPRI v8.8 Rev 1 - pcs_rxdata_chX are "x" when running example design simulation
When I run simulation with the Hard FEC IP example design, pcs_rxdata_chX (rx_out) is always "X".
What can cause this problem?
This is a known issue when using Vivado simulator to simulate the CPRI hard FEC IP example design.
- Vivado 2017.4 - Users can use an alternative simulator to work around the problem.
- Vivado 2018.1 - This issue is resolved in CPRI v8.9 in Vivado 2018.1 and later
For a detailed list of CPRI Release Notes and Known Issues, see (Xilinx Answer 54473).
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