The purpose of this article is to give an explanation of the reported margins after a successful calibration of an UltraScale memory interface in the MIG Dashboard.
In order to have a more complete understanding of what exactly is represented by the Simple and Complex calibration results, please review the calibration section for the specific memory type in the latest version of (PG150):
The margins that are reported in the MIG dashboard actually represent the left and right edges that the FPGA detected as the boundary between the bad and good data regions, while sweeping through the basic and complex calibration steps.
When you have the Centered option selected, it provides the easiest visual representation for you to see this.
It does not mean that those are the absolute edges that were detected for a data transfer, nor does it represent the minimum valid window size for a data transfer.
Because these boundaries represent that the 'FPGA can expect valid data within this region', it is larger than the actual data valid window on the interface.
When you have the Simple calibration pattern selected it does not put a lot of stress on the interface and only uses coarse granularity to determine the valid region.
As a result it can be large compared to the complex calibration.
When you have the Complex calibration pattern selected, it is the final calibration value and overall has a smaller window than the Simple pattern.
The window shrinks because the more advanced calibration steps shrink the eye in which the FPGA can expect valid data.
The next things you need to consider are the Rising and Falling edge conditions, in order to have a better idea of the actual valid window region the FPGA is detecting.
Below is some data from an example to help visualize this. These are the Read Simple margins with the Center view selected.
B0N0 means the Byte 0 Nibble 0 values from the GUI.
Read Simple from the MIG Dashboard:
Rising Left Margin Center Right Margin
B0N0 147 236 147
B0N1 152 233 155
Falling Left Margin Center Right Margin
B0N0 154 218 154
B0N1 155 240 159
Take the Center value and subtract Left Margin to get the Left Window Point.
Take the Center value and add the Right Margin to get the Right Window Point.
Rising Left Window Point Center Right Window Point
B0N0 89 236 383
B0N1 81 233 388
Falling Left Window Point Center Right Window Point
B0N0 64 218 372
B0N1 85 240 399
In the application, the valid window for Byte 0 is now constrained by the largest Left Window Point and the smallest Right Window Point.
Byte 0 = 89ps to 372ps.
This can still be larger than the bit period for the interface, but keep in mind this is the simple calibration pattern, and that this represents the FPGA's expected data valid window based on this calibration step.
When the byte/nibble are showing green it means that the detected window is greater than 30% of the UI bit period.
The yellow byte/nibble simply represents the smallest one detected on the interface.
This does not mean that there is an issue. It just highlights the smallest one.
If the byte/nibble is less than 30% of the bit period, then it will be red.
05/09/2018 - First Release