AR# 71127

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Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit - Pin mapping in Vivado 2018.1 board file part0_pins.xml is incorrect

Description

The Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit pin mapping provided in the Vivado 2018.1 board file part0_pins.xml does not match the hardware.

  1. PL UART pins are swapped.
  2. The GPIO DIP switches are in the VADJ bank (Bank 67) and the IOSTANDARD is set to LVCMOS12. This should be LVCMOS18.

Solution

 

1) PL UART pins are swapped.


Current version:
 
  <pin index="0" name ="uart2_PL_TX" iostandard="LVCMOS12" loc="AH17"/>
  <pin index="1" name ="uart2_PL_RX" iostandard="LVCMOS12" loc="AL17"/> 
 

Correct version:

 
   <pin index="0" name ="uart2_PL_TX" iostandard="LVCMOS12" loc="AL17"/>
   <pin index="1" name ="uart2_PL_RX" iostandard="LVCMOS12" loc="AH17"/> 
   
   

2) The GPIO DIP switches are in the VADJ bank (Bank 67) and the IOSTANDARD is set to LVCMOS12. This should be LVCMOS18.

Current version:

 
  <pin index="124" name ="GPIO_DIP_SW0" iostandard="LVCMOS12" loc="A17"/>
  <pin index="125" name ="GPIO_DIP_SW1" iostandard="LVCMOS12" loc="A16"/>
  <pin index="126" name ="GPIO_DIP_SW2" iostandard="LVCMOS12" loc="B16"/>
  <pin index="127" name ="GPIO_DIP_SW3" iostandard="LVCMOS12" loc="B15"/>
  <pin index="128" name ="GPIO_DIP_SW4" iostandard="LVCMOS12" loc="A15"/>
  <pin index="129" name ="GPIO_DIP_SW5" iostandard="LVCMOS12" loc="A14"/>
  <pin index="130" name ="GPIO_DIP_SW6" iostandard="LVCMOS12" loc="B14"/>
  <pin index="131" name ="GPIO_DIP_SW7" iostandard="LVCMOS12" loc="B13"/>
  
  

Correct version:

 
  <pin index="124" name ="GPIO_DIP_SW0" iostandard="LVCMOS18" loc="A17"/>
  <pin index="125" name ="GPIO_DIP_SW1" iostandard="LVCMOS18" loc="A16"/>
  <pin index="126" name ="GPIO_DIP_SW2" iostandard="LVCMOS18" loc="B16"/>
  <pin index="127" name ="GPIO_DIP_SW3" iostandard="LVCMOS18" loc="B15"/>
  <pin index="128" name ="GPIO_DIP_SW4" iostandard="LVCMOS18" loc="A15"/>
  <pin index="129" name ="GPIO_DIP_SW5" iostandard="LVCMOS18" loc="A14"/>
  <pin index="130" name ="GPIO_DIP_SW6" iostandard="LVCMOS18" loc="B14"/>
  <pin index="131" name ="GPIO_DIP_SW7" iostandard="LVCMOS18" loc="B13"/>
 

Please ensure to update the XDC file with correct settings to match the hardware when the design file is created for ZCU106 using the board file from Vivado 2018.1.

 

This issue is planned to be fixed in a future release of the software.

AR# 71127
Date 05/24/2018
Status Active
Type General Article
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