AR# 71165


Virtex UltraScale+ HBM Controller performance is low when only 1 AXI port is used in a 2 stack design


Version Found: HBM v1.0

Version Resolved: See (Xilinx Answer 69267)

The switch in each stack is clocked by one of the AXI clocks for that stack. 

This is auto-selected by the IP Wizard. If there are 8 AXI ports in use, the Wizard will select a clock that is most centrally located to the enabled AXI ports (this can be overridden by the user by manually selecting a different AXI clock).

In the event that a stack is enabled but no AXI ports are enabled, the software chooses the HBM reference clock which might not be at a frequency ideal for the switch.

Ideally, the switch should run as fast as the fastest AXI clock. 

So in a situation where stack 0 has one AXI port running at 450 MHz, and stack 1 has no AXI ports, the software does not see a AXI clock to use for the switch in stack 1.

As a result it takes the HBM reference clock, which might be at a frequency of less than 450, and therefore creates a performance bottleneck.


The work-around is to enable a single AXI port on the stack with no AXI ports (stack 1 in the example above), ensure that it is running at the same frequency as the AXI port that is in use, and the tools then will automatically select it for use to clock the switch.

This issue will be fixed in the 2018.3 release.

Change Log:

05/30/18 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69267 Virtex UltraScale+ HBM Controller - Release Notes and Known Issues N/A N/A
AR# 71165
Date 06/18/2018
Status Active
Type General Article
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