AR# 7119: V2.1i CORE Generator, SYNPLICITY - CORE Generator does not write out a "/* synthesis black_box */" compiler directive to the VEO file for Synplicity Verilog designs.
AR# 7119
V2.1i CORE Generator, SYNPLICITY - CORE Generator does not write out a "/* synthesis black_box */" compiler directive to the VEO file for Synplicity Verilog designs.
General Description: When Synplicity is specified as the vendor in the CORE Generator, the "//synthesis black_box" compiler directive is not written to the VEO file.
Solution
The /* synthesis black_box */ directive is a Synplicity-specific directive that is not currently supported in the 2.1i CORE Generator VEO file. The vendor setting in the Project Options menu only directs CORE Generator to write out the EDIF implementation netlist for the module with the appropriate EDIF bus delimiter.
Customers must continue to add the /* synthesis black_box */ directive to their designs manually. Please refer to (Xilinx Solution 2713) for examples of how to attach these black box attributes to Verilog designs in Synplicity.
This directive should not be confused with the "// synopsys translate_off" or ''//synopsys translate_on" directives. These latter directives are used to specify that the indicated sections of the .veo file are for behavioral simulation only, and should not be compiled when synthesizing the design.