When the REFCLK frequency is changed from the setting used to create the GT wizard XCI, and the resulting QPLL VCO is operating out of spec range, the QPLL*LOCK output will still assert in simulation.
However, QPLL*LOCK will not assert on hardware.
The behavior is expected. The serial transceiver simulation model does not monitor the QPLL output frequency and does not check if the output frequency matches the expected frequency.
The LOCK output will assert as long as there is a stable output clock.
The GT wizard example design includes the simulation test bench which sets up the expected REFCLK frequency.
The user should not modify the REFCLK frequency on-the-fly, and if a different REFCLK frequency is desired, the GT wizard XCI should be re-configured, and the example design re-generated.
On hardware, QPLL*LOCK fails to assert if the VCO frequency is outside of the VCO operating frequency range.
This is expected behavior for the hardware.