When using the MIPI D-PHY TX, can we assert/de-assert DL*_TXREQUESTHS / CL_TXREQUESTHS at the same time?
Simulation results show that even if the user asserts/de-asserts DL*_TXREQUESTHS / CL_TXREQUESTHS at the same time, the MIPI D-PHY TX can send data correctly.
Asserting DL*_TXREQUESTHS and CL_TXREQUESTHS at the same time is not recommended.
Even if the MIPI D-PHY TX IP seems to sending the correct HS data, we do not guarantee that MIPI D-PHY TX HS-->LP and LP-->HS mode transition will meet the Global operation timing parameter value described in MIPI D-PHY specification v1.1.
MIPI D-PHY TX IP users should consider adding some wait time, to ensure that the IP does not violate the MIPI D-PHY specification.
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