AR# 71205

LogiCORE IP MIPI D-PHY v4.0 - When using MIPI D-PHY TX, can we assert/de-assert DL*_TXREQUESTHS / CL_TXREQUESTHS at the same time?

Description

When using the MIPI D-PHY TX, can we assert/de-assert DL*_TXREQUESTHS / CL_TXREQUESTHS at the same time?

Simulation results show that even if the user asserts/de-asserts DL*_TXREQUESTHS / CL_TXREQUESTHS at the same time, the MIPI D-PHY TX can send data correctly.

Solution

Asserting DL*_TXREQUESTHS and CL_TXREQUESTHS at the same time is not recommended.

Even if the MIPI D-PHY TX IP seems to sending the correct HS data, we do not guarantee that MIPI D-PHY TX HS-->LP and LP-->HS mode transition will meet the Global operation timing parameter value described in MIPI D-PHY specification v1.1.

MIPI D-PHY TX IP users should consider adding some wait time, to ensure that the IP does not violate the MIPI D-PHY specification.

  • after cl_txclkactivehs=high,  wait for CLK-PRE before asserting dl_txrequesths
  • after dl_stopstate=high, wait for CLK-POST before de-asserting cl_txrequesths

 

 



Attachments

Associated Attachments

Name File Size File Type
MIPI_DPHY_TX_mode_transition.png 114 KB PNG

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
AR# 71205
Date 06/07/2018
Status Active
Type General Article
Devices
Tools
IP