This Performance Optimization strategy covers critical design considerations for all applications relying on a traffic pattern of read/write requests issued with very short bursts that impacts on the efficiency of the memory controller.
This includes but is not limited to Video applications using the DDR4 PL IP.
Video applications require a performance optimized memory controller to handle video application throughput and latency requirements.
HEVC and AVC decoders will use a DDR memory accessing pattern that will severely limit the bandwidth/bus-utilization-efficiency of the Xilinx DDR4 controller.
The Zynq UltraScale+ DDR4 PL (MIG) IP is not optimized for video applications, specifically HEVC/AVC codec applications which access DRAM in a block based raster scan order.
In block based raster, read/write requests are issued with very short bursts that impact on the efficiency of the memory controller.
The memory controller efficiency is further reduced if the DRAM interface is designed with x16 components that limit available bank and bank group combinations to 8.
Implementing a DRAM interface with x8 components or dual die x16 components that enable 16 bank + bank group combinations allows users additional bandwidth by reducing the overhead associated with the Xilinx PL DDR4 IP's Group FSM logic.
Any memory address access pattern requiring short bursts or frequently switching bank address pins might benefit from this consideration.
If you are unsure if your DDR interface configuration will meet the system bandwidth targets, see (PG150), Chapter 7: Test Bench
For more information on the DDR4 IP architecture and how banks and bank groups impact overall efficiency see (PG150), Chapter 3: Group Machines, and Chapter 4: Performance.
Note: See (Xilinx Answer 66938) for additional DDR4 restrictions when designing with Twin/Dual die components (x16).