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AR# 71212

2018.2 Vivado IP Release Notes - All IP Change Log Information

Description

This Answer Record contains a comprehensive list of IP change log information from Vivado 2018.2 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

(c) Copyright 2018 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

DISCLAIMER
This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

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100M/1G TSN Subsystem (2.0)

* Version 2.0 (Rev. 1)

* Feature Enhancement: Added parameter to enable 6 byte CB tag feature

* Feature Enhancement: Added disable learning feature on express queue control bit to switch port configuration register

* Revision change in one or more subcores

10G Ethernet MAC (15.1)

* Version 15.1 (Rev. 6)

* Bug Fix: Fixed bug in Example design pattern check module, VHDL version, which resulted in the frame error status signal to be always deasserted

* Bug Fix: Cleaned up lint violations

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 13)

* Revision change in one or more subcores

10G Ethernet Subsystem (3.1)

* Version 3.1 (Rev. 9)

* General: Enabling FB packages for Kintex-7 devices

* Revision change in one or more subcores

10G/25G Ethernet Subsystem (2.4)

* Version 2.4 (Rev. 1)

* Bug Fix: Updated PCS top file for RSFEC connection issue (Xilinx Answer 70945)

* Bug Fix: Updated MAC+PCS/PMA 32-bit file for ports

* Bug Fix: Updated RTL file for license timeout

* Bug Fix: Added XDC constraints for the tools not to optimize the AXI register map counters

* Feature Enhancement: Added support for SDK debugger

* Other: added new devices support

* Revision change in one or more subcores

1G/10G/25G Switching Ethernet Subsystem (2.1)

* Version 2.1

* Port Change: Added new ports for Autonegotiation Support

* Bug Fix: Added XDC constraints for the tools not to optimize the AXI register map counters

* Feature Enhancement: Added Autonegotiation Support

* Feature Enhancement: Added stat_rx_status signal to AXI4Lite register map

* Revision change in one or more subcores

1G/2.5G Ethernet PCS/PMA or SGMII (16.1)

* Version 16.1 (Rev. 4)

* Bug Fix: Updated the rxuserclk/rxuserclk2 clock generation with BUFGCE and CE is connected to MMCM_LOCKED

* Other: Cleared the IntRdEna based on the IntReset assertion

* Other: Added mammoth devices GTY support

* Revision change in one or more subcores

32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 11)

* Added location constraints for xc7a200tsbg484 device

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 15)

* No changes

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 14)

* No changes

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 13)

* No changes

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 17)

* General: Change to assertion in HDL. No change to functionality or performance

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 13)

* No changes

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 14)

* No changes

40G/50G Ethernet Subsystem (2.3)

* Version 2.3 (Rev. 3)

* Bug Fix: Updated example design files for txdiffctrl width fixe

* Bug Fix: Added XDC constraints for the tools not to optimize the AXI register map counters

* Bug Fix: Updated Associated clock interface for 256-bit AXi stream

* Other: added new devices support

* Revision change in one or more subcores

64-bit Initiator/Target for PCI (7 Series) (5.0)

* Version 5.0 (Rev. 11)

* Added location constraints for xc7a200tsbg484 device

7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 9)

* No changes

7 Series Integrated Block for PCI Express (3.3)

* Version 3.3 (Rev. 9)

* Bug Fix: Updated MSIX TABLE & PBA OFFSET parameters. Which effects MSI-X functionality

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 13)

* No changes

AMM Master Bridge (1.0)

* Version 1.0 (Rev. 3)

* General: Updated XPM FIFO instantiation by removing VERSION parameter

* Revision change in one or more subcores

AMM Slave Bridge (1.0)

* Version 1.0 (Rev. 7)

* General: Updated XPM FIFO instantiation by removing VERSION parameter

* Revision change in one or more subcores

AXI 1G/2.5G Ethernet Subsystem (7.1)

* Version 7.1 (Rev. 4)

* Bug Fix: Fixed the local_reset generation for pcs_pma core to 'OR' gate logic for Shared Logic in Example Design configuration: (Xilinx Answer 70875)

* Feature Enhancement: Added support for SDK register debug information

* Other: Refer to tri_mode_ethernet_mac v9_0 and gig_ethernet_pcs_pma v16_1 core change logs for changes in the sub cores of this core

* Revision change in one or more subcores

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 14)

* No changes

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 14)

* No changes

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 14)

* No changes

AXI Bridge for PCI Express Gen3 Subsystem (3.0)

* Version 3.0 (Rev. 7)

* Revision change in one or more subcores

AXI CAN (5.0)

* Version 5.0 (Rev. 20)

* Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 17)

* Revision change in one or more subcores

AXI Chip2Chip Bridge (5.0)

* Version 5.0 (Rev. 3)

* Bug Fix: IP updated to handle SelectIO link up issues between 7 Series and UltraScale/UltraScale+ architectures

* Bug Fix: AXI4 Lite Base and High address exported to SDK

* Other: XDCs updated for runtime improvement

* Revision change in one or more subcores

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 16)

* Revision change in one or more subcores

AXI Crossbar (2.1)

* Version 2.1 (Rev. 18)

* General: When DECERR, it returns RDATA=0xDEC0DE1C

* Revision change in one or more subcores

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 16)

* Revision change in one or more subcores

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 17)

* Revision change in one or more subcores

AXI DataMover (5.1)

* Version 5.1 (Rev. 19)

* General: Updates to example design XDC file

* General: Enhanced support for IP Integrator

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 18)

* Bug Fix: Fixed the S2MM AXIS propagation issue for TDATA width of 1 and 2 bytes

* Bug Fix: Restored the BRAM utilization issue observed in 2018.1 release

* Revision change in one or more subcores

AXI EMC (3.0)

* Version 3.0 (Rev. 17)

* Revision change in one or more subcores

AXI EPC (2.0)

* Version 2.0 (Rev. 20)

* Revision change in one or more subcores

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 18)

* No changes

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes

AXI EthernetLite (3.0)

* Version 3.0 (Rev. 15)

* Revision change in one or more subcores

AXI GPIO (2.0)

* Version 2.0 (Rev. 19)

* Revision change in one or more subcores

AXI HWICAP (3.0)

* Version 3.0 (Rev. 21)

* Revision change in one or more subcores

AXI IIC (2.0)

* Version 2.0 (Rev. 20)

* Revision change in one or more subcores

AXI Interconnect (2.1)

* Version 2.1 (Rev. 18)

* Revision change in one or more subcores

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 11)

* General: Avoid warning for IVAR reset value 0x80000000 or greater

* General: Updated HDL to avoid lint error. No functional change.

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 4)

* No changes

AXI MMU (2.1)

* Version 2.1 (Rev. 15)

* Revision change in one or more subcores

AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Memory Mapped To PCI Express (2.8)

* Version 2.8 (Rev. 9)

* Bug Fix: Updated MSIX TABLE & PBA OFFSET parameters. Which effects MSI-X functionality

* Other: Updated MPS value to 256 Bytes in simulation (512 Bytes is not supported by this IP)

* Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 16)

* Revision change in one or more subcores

AXI Multi Channel Direct Memory Access (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 19)

* General: Bug fix for Tvalid assertion on trace output

* Revision change in one or more subcores

AXI Protocol Checker (2.0)

* Version 2.0 (Rev. 3)

* Revision change in one or more subcores

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 17)

* Revision change in one or more subcores

AXI Protocol Firewall (1.0)

* Version 1.0 (Rev. 5)

* General: Firewall trips, it returns RDATA=0xDEADFA11

* Revision change in one or more subcores

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 16)

* General: Updated Maximum ID width support to 32

* Revision change in one or more subcores

AXI Register Slice (2.1)

* Version 2.1 (Rev. 17)

* New Feature: Added USER_SLL_REG attributes to automatically improve QOR of Multi-SLR-crossing mode.

* Revision change in one or more subcores

AXI Sideband Utility (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

AXI SmartConnect (1.0)

* Version 1.0 (Rev. 9)

* Bug Fix: Fixed windows-specific issue where routing of transactions might be incorrect when address widths are greater than 32-bit

* Revision change in one or more subcores

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 20)

* No changes

AXI Timebase Watchdog Timer (3.0)

* Version 3.0 (Rev. 9)

* Revision change in one or more subcores

AXI Timer (2.0)

* Version 2.0 (Rev. 19)

* Revision change in one or more subcores

AXI Traffic Generator (3.0)

* Version 3.0 (Rev. 3)

* Revision change in one or more subcores

AXI UART16550 (2.0)

* Version 2.0 (Rev. 19)

* Revision change in one or more subcores

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 18)

* Revision change in one or more subcores

AXI Uartlite (2.0)

* Version 2.0 (Rev. 21)

* Revision change in one or more subcores

AXI Verification IP (1.1)

* Version 1.1 (Rev. 3)

* General: fixed typo in example design stimulus

* Revision change in one or more subcores

AXI Video Direct Memory Access (6.3)

* Version 6.3 (Rev. 5)

* Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 19)

* Revision change in one or more subcores

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 14)

* Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 13)

* No changes

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 16)

* Revision change in one or more subcores

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 18)

* Revision change in one or more subcores

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 15)

* Revision change in one or more subcores

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 18)

* Revision change in one or more subcores

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 16)

* Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 18)

* Revision change in one or more subcores

AXI4-Stream Protocol Checker (2.0)

* Version 2.0 (Rev. 1)

* Revision change in one or more subcores

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 17)

* New Feature: Added USER_SLL_REG attributes to automatically improve QOR of Multi-SLR-crossing mode.

* Revision change in one or more subcores

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 17)

* Revision change in one or more subcores

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 17)

* Revision change in one or more subcores

AXI4-Stream Verification IP (1.1)

* Version 1.1 (Rev. 3)

* General: modify instance pkg generation so there is no mismatch between interface and virtual interface

* Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 9)

* No changes

Accumulator (12.0)

* Version 12.0 (Rev. 12)

* No changes

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 12)

* No changes

Aurora 64B66B (11.2)

* Version 11.2 (Rev. 5)

* Bug Fix: Changed logic to transmit invalid headers during PMA_INIT assertion to ensure that link partner loses block sync.

* Bug Fix: Aurora TX,RX clocking helper blocks updated to match that of UltraScale GT Wizard IP.

* Bug Fix: Modified logic to assert GT RX Datapath Reset when Hard error occurs.

* Bug Fix: Fixed core generation issues when targeting the IP to QVIRTEXUPLUS and QZYNQUPLUS devices.

* Revision change in one or more subcores

Aurora 8B10B (11.1)

* Version 11.1 (Rev. 5)

* Bug Fix: Fixed display only issue showing improper clock frequencies for tx_out_clk and sync_clk in IP Integrator flow for GTP devices.

* Revision change in one or more subcores

Binary Counter (12.0)

* Version 12.0 (Rev. 12)

* No changes

Block Memory Generator (8.4)

* Version 8.4 (Rev. 1)

* No changes

CANFD (1.0)

* Version 1.0 (Rev. 10)

* General: Device support added, no functional changes

* Revision change in one or more subcores

CIC Compiler (4.0)

* Version 4.0 (Rev. 13)

* No changes

CORDIC (6.0)

* Version 6.0 (Rev. 14)

* No changes

CPRI (8.9)

* Version 8.9 (Rev. 1)

* Bug Fix: Fixed example design HDLC stimulus block reset issue.

* Bug Fix: Fixed example design Hard FEC Wrapper data checker bug.

* Other: Added support for new virtexusplus58g family.

* Revision change in one or more subcores

Chroma Resampler (4.0)

* Version 4.0 (Rev. 13)

* No changes

Clock Verification IP (1.0)

* Version 1.0 (Rev. 1)

* No changes

Clocking Wizard (6.0)

* Version 6.0 (Rev. 1)

* Bug Fix: Removed vco freq check when Primitive is None

* Other: New family support added

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 14)

* No changes

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 13)

* No changes

Compact GT (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

Complex Multiplier (6.0)

* Version 6.0 (Rev. 15)

* No changes

Concat (2.1)

* Version 2.1 (Rev. 1)

* No changes

Constant (1.1)

* Version 1.1 (Rev. 5)

* Added tooltip about the radix values that are supported (decimal/hexadecimal(Ox)/octal(0)/binary(Ob/b))

* SystemC simulation support

Convolution Encoder (9.0)

* Version 9.0 (Rev. 13)

* No changes

DDR3 SDRAM (MIG) (1.4)

* Version 1.4 (Rev. 5)

* Revision change in one or more subcores

DDR4 SDRAM (MIG) (2.2)

* Version 2.2 (Rev. 5)

* General: Updated for 2018.2

* Revision change in one or more subcores

DDS Compiler (6.0)

* Version 6.0 (Rev. 16)

* No changes

DMA/Bridge Subsystem for PCI Express (PCIe) (4.1)

* Version 4.1 (Rev. 1)

* Bug Fix: Allowed AXI-MM Bypass BAR size till 256GB for 64bit BAR (Xilinx Answer 71012)

* Bug Fix: Removed dependency of 'GT Channel DRP' parameter on 'Enable In System IBERT' parameter. Now, both the options can be selected at the same time

* Bug Fix: Slave AXI Lite memory range is updated to 64KB for DMA functional mode and 512MB for AXI Bridge functional mode

* Bug Fix: Fixed Posted TLP ordering issue on Slave AXI Lite and Slave AXI interfaces

* Bug Fix: Fixed Master MemWr and received interrupt ordering issue for AxiBridge RC configuration

* Bug Fix: Fix for CQ NP credits after Partial Reconfiguration

* Bug Fix: Fixed 7 Series Gen2 DMA hang issue due to TLP drop and incorrect TLP for straddled packets

* Feature Enhancement: Enabled x16g3 configuration support for -1 speedgrade of UltraScale+ family devices

* Other: Performance improved for AXI bridge slave interface (Xilinx Answer 71052)

* Other: Added support for the defense grade devices xqvu7p,xqvu11p,xqzu5ev,xqzu7ev,xqzu19eg,xqzu21dr and xqzu28dr

* Other: Added support for xcvu29p device

* Revision change in one or more subcores

DSP48 Macro (3.0)

* Version 3.0 (Rev. 16)

* No changes

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 14)

* No changes

Debug Bridge (3.0)

* Version 3.0 (Rev. 3)

* General: Added device support for virtexuplus58g family

* Revision change in one or more subcores

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 15)

* No changes

DisplayPort (8.0)

* Version 8.0 (Rev. 1)

* Bug Fix: Auto library update

* Revision change in one or more subcores

DisplayPort RX Subsystem (2.1)

* Version 2.1 (Rev. 3)

* Revision change in one or more subcores

DisplayPort TX Subsystem (2.1)

* Version 2.1 (Rev. 3)

* Revision change in one or more subcores

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 12)

* No changes

Divider Generator (5.1)

* Version 5.1 (Rev. 13)

* No changes

Double Data Rate Sampling (1.0)

* Version 1.0

* No changes

ECC (2.0)

* Version 2.0 (Rev. 12)

* No changes

ETRNIC (1.1)

* Version 1.1

* General: Removed some un-used memory mapped registers

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 19)

* Revision change in one or more subcores

FEC 5G Common Utilities (1.1)

* Version 1.1

* No changes

FIFO Generator (13.2)

* Version 13.2 (Rev. 2)

* No changes

FIR Compiler (7.2)

* Version 7.2 (Rev. 11)

* No changes

Fast Fourier Transform (9.1)

* Version 9.1

* No changes

Fibre Channel 32GFC RS-FEC (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 8)

* No changes

FlexO 100G RS-FEC (1.0)

* Version 1.0 (Rev. 7)

* Bug Fix: Fixed example design issue on Windows platform, in which alignment markers were incorrectly truncated: (Xilinx Answer 70941)

* Revision change in one or more subcores

Floating-point (7.1)

* Version 7.1 (Rev. 6)

* No changes

G.709 FEC Encoder/Decoder (2.3)

* Version 2.3 (Rev. 3)

* General: bugfix for GUI. No change to interfaces, form or functionality.

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 15)

* No changes

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 17)

* No changes

Gamma Correction (7.0)

* Version 7.0 (Rev. 14)

* No changes

Gamma LUT (1.0)

* Version 1.0 (Rev. 3)

* General: Updated synthesizable example design.  For 4 and 8 samples per clock, the video clock frequency has changed from 297 MHz to 148.5 MHz and the video stream clock has changed from 300 MHz to 150 MHz.

* Revision change in one or more subcores

Gmii to Rgmii (4.0)

* Version 4.0 (Rev. 6)

* No changes

HBM IP (1.0)

* Version 1.0 (Rev. 1)

* General: Updated for 2018.2

HDCP (1.0)

* Version 1.0 (Rev. 3)

* No changes

HDCP 2.2 Cipher (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDCP 2.2 Montgomery Modular Multipiler (1.0)

* Version 1.0 (Rev. 2)

* No changes

HDCP 2.2 Random Number Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes

HDCP 2.2 Receiver (1.0)

* Version 1.0 (Rev. 6)

* No changes

HDCP 2.2 Transmitter (1.0)

* Version 1.0 (Rev. 6)

* No changes

HDMI 1.4/2.0 Receiver (3.0)

* Version 1.1

* No changes

HDMI 1.4/2.0 Receiver Subsystem (3.1)

* Version 3.1

* No changes

HDMI 1.4/2.0 Transmitter (3.0)

* Version 2.0

* No changes

HDMI 1.4/2.0 Transmitter Subsystem (3.1)

* Version 3.1

* No changes

High Speed SelectIO Wizard (3.4)

* Version 3.4

* New Feature: Added new feature "Enable DRP ports of PLL" to bring up the DRP ports of PLL

* Feature Enhancement: Async Mode state is changed from Beta to Production

* Other: Async Mode data speed is limited to 1300Mbps (max)

I2S Receiver (1.0)

* Version 1.0 (Rev. 1)

* General: Updated example design by pushing AXIS and AXI4 generation logic inside synthesizable example design top module.

I2S Transmitter (1.0)

* Version 1.0 (Rev. 1)

* General: Fixes to identify error scenarios on AXIS input

* General: Updates to example design

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 17)

* No changes

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 17)

* No changes

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 17)

* No changes

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 15)

* No changes

IBERT Ultrascale GTH (1.4)

* Version 1.4

* Bug Fix: Updated IO standards for system clock when DIFF TERM is enabled

* Revision change in one or more subcores

IBERT UltraScale GTY (1.3)

* Version 1.3

* Bug Fix: Fixed issue to enable diff term selected during IP customization

* Revision change in one or more subcores

IEEE 802.3 200G RS-FEC (1.0)

* Version 1.0 (Rev. 3)

* General: Brings dynamic skew tolerance adjustment control out to top level as requested by EISG.

* Revision change in one or more subcores

IEEE 802.3 25G RS-FEC (1.0)

* Version 1.0 (Rev. 9)

* Bug Fix: Fixed example design issue on Windows platform, in which alignment markers were incorrectly truncated: (Xilinx Answer 70941)

* Revision change in one or more subcores

IEEE 802.3 400G RS-FEC (1.0)

* Version 1.0 (Rev. 3)

* General: Brings dynamic skew tolerance adjustment control out to top level as requested by EISG.

* Revision change in one or more subcores

IEEE 802.3 50G RS-FEC (1.0)

* Version 1.0 (Rev. 9)

* Bug Fix: Fixed example design issue on Windows platform, in which alignment markers were incorrectly truncated: (Xilinx Answer 70941)

* Revision change in one or more subcores

IEEE 802.3 Clause 74 FEC (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

IEEE 802.3bj 100G RS-FEC (2.0)

* Version 2.0 (Rev. 1)

* Bug Fix: Fixed example design issue on Windows platform, in which alignment markers were incorrectly truncated: (Xilinx Answer 70941)

* Revision change in one or more subcores

ILA (Integrated Logic Analyzer) (6.2)

* Version 6.2 (Rev. 7)

* General: Added device support for virtexuplus58gf family

IOModule (3.1)

* Version 3.1 (Rev. 3)

* No changes

Image Enhancement (8.0)

* Version 8.0 (Rev. 14)

* No changes

In System IBERT (1.0)

* Version 1.0 (Rev. 7)

* General: Added support for 58 Gig device.

* Revision change in one or more subcores

Interlaken 150G (2.4)

* Version 2.4 (Rev. 1)

* Bug Fix: Updated header file with register information

* Bug Fix: Added XDC constraints for the tools not to optimize the AXI register map counters

* Other: added new devices support

* Revision change in one or more subcores

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 12)

* No changes

JESD204 (7.2)

* Version 7.2 (Rev. 3)

* Feature Enhancement: Added support for virtexuplus58g device family

* Revision change in one or more subcores

JESD204 PHY (4.0)

* Version 4.0 (Rev. 3)

* Feature Enhancement: Added support for virtexuplus58g device family

* Revision change in one or more subcores

JESD204C (3.0)

* Version 3.0 (Rev. 1)

* Bug Fix: Corrected an issue in the example design where the refclk ports would not be connected if the core was generated to use a QPLL

* Feature Enhancement: Added support for virtexuplus58g device family

* Revision change in one or more subcores

JTAG to AXI Master (1.2)

* Version 1.2 (Rev. 7)

* General: virtexuplus58g device support added

LDPC Encoder/Decoder (2.0)

* Version 2.0 (Rev. 1)

* Bug Fix: Correction to C model Offset Min-Sum implementation, (Xilinx Answer 71036).

* Bug Fix: Improve example design AWGN channel accuracy.

* Bug Fix: Resolve example design CDC critical warnings on the interrupt signals.

LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 15)

* General: Added support for Virtex UltraScale+ 58g devices

LPDDR3 SDRAM (MIG) (1.0)

* Version 1.0 (Rev. 5)

* General: Changes for 2018.2

* Revision change in one or more subcores

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 14)

* No changes

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 16)

* No changes

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 14)

* No changes

LTE RACH Detector (3.1)

* Version 3.1 (Rev. 3)

* General: Optimization to DCC filters. No change to functionality, but resources will be saved.

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 14)

* No changes

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 9)

* No changes

MIPI CSI-2 Rx Controller (1.0)

* Version 1.0 (Rev. 8)

* No changes

MIPI CSI-2 Rx Subsystem (3.0)

* Version 3.0 (Rev. 3)

* Revision change in one or more subcores

MIPI CSI-2 Tx Controller (1.0)

* Version 1.0 (Rev. 4)

* No changes

MIPI CSI-2 Tx Subsystem (2.0)

* Version 2.0 (Rev. 3)

* Revision change in one or more subcores

MIPI D-PHY (4.1)

* Version 4.1 (Rev. 1)

* Bug Fix: Minor bug fix for IP generation with some Spartan-7 parts

* Revision change in one or more subcores

MIPI DSI Tx Controller (1.0)

* Version 1.0 (Rev. 6)

* No changes

MIPI DSI Tx Subsystem (2.0)

* Version 2.0 (Rev. 3)

* Revision change in one or more subcores

Mailbox (2.1)

* Version 2.1 (Rev. 10)

* General: Updated HDL to avoid lint error. No functional change.

Memory Helper Core (1.4)

* Version 1.4

* No changes

Memory Interface Generator (MIG 7 Series) (4.1)

* Version 4.1

* No changes

MicroBlaze (10.0)

* Version 10.0 (Rev. 7)

* Bug Fix: Handle Ext_NM_BRK exception independent of whether Ext_BRK is connected or not. Versions that have this issue: 7.10.a-10.0. Can only occur with performance optimization when Ext_BRK is not connected.

* Other: Added support for Virtex UltraScale+ 58g devices

* Other: Updated HDL to avoid lint errors. No functional change.

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 14)

* General: Improve clocking for Xilinx Virtual Cable (XVC) debug connection

MicroBlaze MCS (3.0)

* Version 3.0 (Rev. 9)

* General: Added support for Virtex UltraScale+ 58g devices

* Revision change in one or more subcores

Multiplier (12.0)

* Version 12.0 (Rev. 14)

* No changes

Multiply Adder (3.0)

* Version 3.0 (Rev. 12)

* No changes

Mutex (2.1)

* Version 2.1 (Rev. 9)

* General: Corrected HDL to remove multiple simultaneous drivers.

PCIe PHY IP (1.0)

* Version 1.0 (Rev. 9)

* Bug Fix: Enabled txprgdivresetdone_out port from GT Wizard to fix issue when reference clock is 125/250 MHz

* Revision change in one or more subcores

PR AXI Shutdown Manager (1.0)

* Version 1.0

* No changes

PR Bitstream Monitor (1.0)

* Version 1.0

* No changes

Partial Reconfiguration Controller (1.3)

* Version 1.3 (Rev. 1)

* Bug Fix: Fixed a bug in the status.  The FULL state was reported before the RM_RESET was complete

Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 6)

* Bug Fix: Widths did not propagate from all interface pins on a partition def

Peak Cancellation Crest Factor Reduction (6.2)

* Version 6.2

* Feature Enhancement: HW Optimization by changing 4-DSP48 complex Multiplier to 3-DSP48 Complex Multiplier.

* Feature Enhancement: Support of 16-Antenna.

Polar Encoder/Decoder (1.0)

* Version 1.0 (Rev. 1)

* Bug Fix: Improve example design AWGN channel accuracy.

Processor System Reset (5.0)

* Version 5.0 (Rev. 12)

* No changes

QDRII+ SRAM (MIG) (1.4)

* Version 1.4 (Rev. 5)

* General: Updated for 2018.2

* Revision change in one or more subcores

QDRIV SRAM (MIG) (2.0)

* Version 2.0 (Rev. 5)

* Revision change in one or more subcores

QDRIV SRAM PHY IP (2.0)

* Version 1.2

* No changes

QSGMII (3.4)

* Version 3.4 (Rev. 4)

* General: Added support for Defense Zynq UltraScale+ devices

* Revision change in one or more subcores

Queue DMA Subsystem for PCI Express (PCIe) (2.0)

* Version 2.0

* Feature Enhancement: Major updates and functional fixes.

* Feature Enhancement: Added awuser, aruser signals on m_axil and m_axib interfaces.

* Feature Enhancement: Added soft_reset_n input port.

* Revision change in one or more subcores

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 12)

* No changes

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 12)

* No changes

RLDRAM3 (MIG) (1.4)

* Version 1.4 (Rev. 5)

* Revision change in one or more subcores

RXAUI (4.4)

* Version 4.4 (Rev. 4)

* Bug Fix: Lint checks

* Other: Support for Defense grade Zynq UltraScale+ devices

* Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 14)

* No changes

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 13)

* No changes

Reset Verification IP (1.0)

* Version 1.0 (Rev. 1)

* No changes

SC EXIT (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores

SC MMU (1.0)

* Version 1.0 (Rev. 6)

* General: When DECERR, it returns RDATA=0xDEC0DEE3

* Revision change in one or more subcores

SC SI_CONVERTER (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores

SC SPLITTER (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

SC TRANSACTION_REGULATOR (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores

SDI RX to Video Bridge (2.0)

* Version 2.0

* No changes

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 8)

* No changes

SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 5)

* No changes

SMPTE UHD-SDI RX (1.0)

* Version 1.0

* No changes

SMPTE UHD-SDI RX SUBSYSTEM (2.0)

* Version 2.0 (Rev. 1)

* Bug Fix: Fixed RTL compilation warnings

* Revision change in one or more subcores

SMPTE UHD-SDI TX (1.0)

* Version 1.0

* No changes

SMPTE UHD-SDI TX SUBSYSTEM (2.0)

* Version 2.0 (Rev. 1)

* Bug Fix: Fixed RTL compilation warnings

* Revision change in one or more subcores

SPDIF/AES3 (2.0)

* Version 2.0 (Rev. 19)

* No changes

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 12)

* General: Properly tied off the undriven input ports

Sensor Demosaic (1.0)

* Version 1.0 (Rev. 3)

* General: Updated synthesizable example design.  For 4 and 8 samples per clock, the video clock frequency has changed from 297 MHz to 148.5 MHz and the video stream clock has changed from 300 MHz to 150 MHz.

* Revision change in one or more subcores

Serial RapidIO Gen2 (4.1)

* Version 4.1 (Rev. 4)

* Feature Enhancement: Added support for Qvirtexuplus and virtexuplus58G families

* Revision change in one or more subcores

SmartConnect AXI2SC Bridge (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores

SmartConnect Node (1.0)

* Version 1.0 (Rev. 9)

* Bug Fix: disable xpm_cdc_handshake drc checks during reset

* Bug Fix: Enable register init option on xpm_cdc_gray to resolve undefined values in simulation.

* Revision change in one or more subcores

SmartConnect SC2AXI Bridge (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores

SmartConnect Switchboard (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 11)

* No changes

Soft-Decision FEC (1.1)

* Version 1.1 (Rev. 1)

* Bug Fix: Improve example design AWGN channel accuracy.

* Feature Enhancement: Runtime Loading GUI tab updated to reflect changes in XPE and Vivado Report Power, (Xilinx Answer 71060)

Switch Core Top (1.0)

* Version 1.0 (Rev. 5)

* No changes

System Cache (4.0)

* Version 4.0 (Rev. 5)

* Bug Fix: Corrected statistics read for ports 8 - 15

* Other: Added support for Virtex UltraScale+ 58g devices

* Other: Updated HDL to avoid lint errors. No functional change.

System ILA (1.1)

* Version 1.1 (Rev. 3)

* General: Device support added for virtexuplus58G family

* Revision change in one or more subcores

System Management Wizard (1.3)

* Version 1.3 (Rev. 8)

* Feature Enhancement: Feature to enable the Under temperature alarms is added.

* Other: Internal GUI change. No affect to the customers.

TMR Comparator (1.0)

* Version 1.0 (Rev. 1)

* No changes

TMR Inject (1.0)

* Version 1.0 (Rev. 2)

* No changes

TMR Manager (1.0)

* Version 1.0 (Rev. 3)

* No changes

TMR Soft Error Mitigation Interface (1.0)

* Version 1.0 (Rev. 5)

* General: Updated HDL to avoid lint error. No functional change.

* Revision change in one or more subcores

TMR Voter (1.0)

* Version 1.0 (Rev. 1)

* No changes

TSN Endpoint Block (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

TSN Tri Mode Ethernet MAC (1.0)

* Version 1.0 (Rev. 3)

* No changes

Time-Aware DMA (1.0)

* Version 1.0 (Rev. 1)

* RTL Fixes

* Revision change in one or more subcores

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 4)

* No changes

Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 12)

* Bug Fix: Assign initial value to user parameter int_clk_src

* Bug Fix: Cleaned up lint violations

* Other: New device support

UHD-SDI Audio (1.1)

* Version 1.1

* Bug Fix: SD-SDI Audio Embed: Sample Rate in Control Packet can now be configured through configuration interface (Previously it was fixed at 48 Khz)

* Bug Fix: SD-SDI Audio Embed: Group ordering issue resolved. Example : 4 Channel system can now be configured to work on Group 2 or 3 or 4 (Previously the 4 channel system only work on Group 1, etc)

* Bug Fix: SD-SDI Audio Embed/Extract: When control packet is optional/missing, the audio group detect module reports active channel information decoded from the data packet

* Bug Fix: In 2, 6, 10 & 14 channel system, remaining 2 channels in the last group are sent with mute data with valid bit set to 1 (Previously only the control packet conveyed the inactive channels)

* Bug Fix: Audio Embed : Fixed the rate control logic (Transmission of samples is controlled with respect to the Audio Sample Rate, Video Frame Rate & Resolution)

* Bug Fix: Fixed RTL Compilation Warnings

* Other: UHD-SDI Audio Category changed to Audio Connectivity & Processing

* Other: Default value of reserved register at offset 0x8 is changed to 0x0 to be in sync with other reserved registers (Previously, it was 0x1)

UHD-SDI GT (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Fixed multi-link GT instantiation issue

UHD-SDI Video Pattern Generator (1.0)

* Version 1.0

* No changes

UltraScale 100G Ethernet Subsystem (2.3)

* Version 2.3 (Rev. 3)

* Port Change: Added user_reg0 port when AXI4-lite is enabled

* Port Change: Enabled the gt_rxusrclk2 port for default option

* Other: Added USER_REG0 register with address 0x00CC for user access

* Other: Registered the tx_reset_done and rx_reset_done as these are the outputs from the IP in case of Shared Logic in Example Design

* Other: Added XDC constraints for the tools not to optimize the AXI register map counters

* Revision change in one or more subcores

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)

* Version 4.4 (Rev. 3)

* Bug Fix: Removed dependency of 'GT Channel DRP' parameter on 'Enable In System IBERT' parameter. Now, both the options can be selected at the same time

* Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.7)

* Version 1.7 (Rev. 4)

* General: Removed the XDC work-around in place for In-System IBERT rxrate ports

* Revision change in one or more subcores

UltraScale Soft Error Mitigation (3.1)

* Version 3.1 (Rev. 8)

* Bug Fix: Fix slr2_cfg_frame_ecce4 primitive location constraint in the example design for vu37p

* Other: Added support for Defense-Grade UltraScale+ devices

UltraScale+ 100G Ethernet Subsystem (2.4)

* Version 2.4 (Rev. 3)

* Port Change: Added user_reg0 port when AXI4-lite is enabled

* Port Change: Enabled the gt_rxusrclk2 port for default option

* Other: Added USER_REG0 register with address 0x00CC for user access

* Other: Registered the tx_reset_done and rx_reset_done as these are the outputs from the IP in case of Shared Logic in Example Design

* Other: Added new UltraScale+ devices support

* Other: Added XDC constraints for the tools not to optimize the AXI register map counters

* Revision change in one or more subcores

UltraScale+ PCI Express 4c Integrated Block (1.0)

* Version 1.0 (Rev. 3)

* Feature Enhancement: The Virtual Channel(VC) Capability by default enabled

* Revision change in one or more subcores

UltraScale+ PCI Express Integrated Block (1.3)

* Version 1.3 (Rev. 3)

* Feature Enhancement: Enhancement in PIO Example Design to support multiple DWORD transaction.

* Revision change in one or more subcores

Universal Serial XGMII Ethernet Subsystem (1.0)

* Version 1.0 (Rev. 3)

* Bug Fix: Cleaned up lint violations

* Bug Fix: Fixed bug which resulted in the GT DRP, status and control ports not being connected to GT inputs when the core is generated with Additional GT control/status and DRP ports option

* Other: New device support

* Other: Added dont_touch synthesis attribute to modules having AXI4-Lite bus interface. This will prevent optimization of control/status registers when example design is implemented and thus resource utilization data will be accurate

* Revision change in one or more subcores

Utility Reduced Logic (2.0)

* Version 2.0 (Rev. 4)

* No changes

Utility Vector Logic (2.0)

* Version 2.0 (Rev. 1)

* No changes

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 19)

* General: virtexuplus58g device support added

Video AXI4S Remapper (1.0)

* Version 1.0 (Rev. 9)

* Revision change in one or more subcores

Video Color Space Conversion and Correction (1.0)

* Version 1.0 (Rev. 11)

* General: Updated synthesizable example design

* Revision change in one or more subcores

Video Deinterlacer (5.0)

* Version 5.0 (Rev. 11)

* New Feature: Added more values for C_AXIMM_BURST_LENGTH

* Revision change in one or more subcores

Video DisplayPort 1.4 RX Subsystem (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

Video DisplayPort 1.4 TX Subsystem (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

Video Frame Buffer Read (2.1)

* Version 2.1

* General: Updated Linux driver for interlaced support

* Revision change in one or more subcores

Video Frame Buffer Write (2.1)

* Version 2.1

* General: Updated Linux driver for interlaced support

* Revision change in one or more subcores

Video Horizontal Chroma Resampler (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores

Video Horizontal Scaler (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores

Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 8)

* No changes

Video Letterbox Engine (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores

Video Mixer (3.0)

* Version 3.0 (Rev. 1)

* New Feature: Added ability to flush pending AXI transactions before reset

* Revision change in one or more subcores

Video On Screen Display (6.0)

* Version 6.0 (Rev. 15)

* No changes

Video PHY Controller (2.2)

* Version 2.2 (Rev. 1)

* General: Extended GTYE4 supports for HDMI protocol on Virtex UltraScale + 58G and HBM device family

* Revision change in one or more subcores

Video Processing Subsystem (2.0)

* Version 2.0 (Rev. 9)

* General: Updated synthesizable example design

* Revision change in one or more subcores

Video Test Pattern Generator (7.0)

* Version 7.0 (Rev. 11)

* General: Updated synthesizable example design

* Revision change in one or more subcores

Video Timing Controller (6.1)

* Version 6.1 (Rev. 12)

* No changes

Video Vertical Chroma Resampler (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores

Video Vertical Scaler (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores

Video to SDI TX Bridge (2.0)

* Version 2.0

* No changes

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)

* Version 4.3 (Rev. 3)

* Bug Fix: Updated MSIX TABLE & PBA OFFSET parameters. Which effects MSI-X functionality

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 9)

* No changes

XADC Wizard (3.3)

* Version 3.3 (Rev. 5)

* No changes

XAUI (12.3)

* Version 12.3 (Rev. 4)

* General: Support for Defense grade Zynq UltraScale+ devices

* Revision change in one or more subcores

XHMC (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 12)

* No changes

ZYNQ UltraScale+ VCU (1.1)

* Version 1.1 (Rev. 1)

* Port Change: NONE

* Bug Fix: BValid Toggle fix in RTL

* Bug Fix: Fix for Smart Interconnect optimization

* Feature Enhancement: NONE

* Other: NONE

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 6)

* No changes

ZYNQ7 Processing System VIP (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores

ZYNQMPSOC Processing System VIP (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

Zynq UltraScale+ MPSoC (3.2)

* Version 3.2 (Rev. 1)

* Bug Fix: 1. SD0_8BIT field of SD_CONFIG_REG2(0xFF180320) register will be updated based on SD data transfer mode (4Bit/8Bit).

* Bug Fix: 2. Fixed incorrect power report calculation for CG devices.

* Revision change in one or more subcores

Zynq UltraScale+ RF Data Converter (2.0)

* Version 2.0 (Rev. 1)

* Bug Fix: Fixed DAC PLL Vco range for sampling rates above 6.4GSPS

* Bug Fix: Set max ADC sampling rate to 4.096GHz for ZU25/27/28DR devices

* Bug Fix: Fix issue with Multi Tile SYNC sysref counters. Previous counters could fail to meet the minimum threshold value

* Bug Fix: Fixed issue with the opening of the example design in Windows

* Bug Fix: Updated PLL VREG setting

* Feature Enhancement: Improved AXI to DRP access times

* Feature Enhancement: Disabled interpolation filter on unused paths

* Feature Enhancement: Removed LUTAR methodology warning

* Feature Enhancement: Implemented new PLL lock procedure

* Feature Enhancement: Wait for de-assertion of AXI-Streaming reset before completing start-up

* Other: Changed example design name to rfdc_ex to reduce path lengths

* Other: Increased minimum PLL reference clock from 50MHz to 102.4062MHZ

audio_tpg_v1_0 (1.0)

* Version 1.0

* No changes

axi_msg (1.0)

* Version 1.0 (Rev. 3)

* General: XPM FIFO reset fixes

axi_sg (4.1)

* Version 4.1 (Rev. 10)

* Updates to fix XPM FIFO reset

interrupt_controller (3.1)

* Version 3.1 (Rev. 4)

* No changes

lib_bmg (1.0)

* Version 1.0 (Rev. 10)

* No changes

lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_fifo (1.0)

* Version 1.0 (Rev. 11)

* No changes

lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes

AR# 71212
Date 06/28/2018
Status Active
Type Release Notes
Tools
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