Version Found: HBM v1.0
Version Resolved: See (Xilinx Answer 69267)
When using Engineering Sample Virtex UltraScale+ HBM devices, there is a possibility that a cross stack transaction can hang in the inter-stack channels.
When a read or a write command is sent from an AXI port that crosses from one HBM stack to the other through the AXI Switch, the command fails to propagate.
No error flag or normal response is returned to the AXI port.
The AXI port will ultimately hang as it waits for a response that will never come.
A device that works for some time does not mean that the device is immune to the problem as this can occur with any cross stack transaction.
This behavior is fixed in silicon in production Virtex UltraScale+ HBM devices.
For Engineering Sample devices you can avoid this lockup by not issuing any cross stack transactions.
Both stacks can be enabled and as long as a cross stack transaction does not occur then you will not encounter the hang.
If cross stack transactions are required, use the following work-around:
set_clock_groups -logically_exclusive -group [get_clocks AXI_ACLK*_st0 ] -group [get_clocks o_APB_PCLK_by8_st0 ]
set_clock_groups -logically_exclusive -group [get_clocks AXI_ACLK*_st1 ] -group [get_clocks o_APB_PCLK_by8_st1 ]
|01/06/2019||Updated with 2018.3 patch files|
|08/23/2019||Updated with 2019.1 patch files|