AR# 71312


Virtex UltraScale+ HBM FPGA XCVU31P, XCVU33P, XCVU35P, XCVU37P ES983x – A cross stack transaction can hang the inter-stack channels


Version Found: HBM v1.0

Version Resolved: See (Xilinx Answer 69267)

When using Engineering Sample Virtex UltraScale+ HBM devices, there is a possibility that a cross stack transaction can hang in the inter-stack channels.

The potential hang can only occur when all of the following conditions are true:
  • Using Virtex UltraScale+ HBM Engineering Sample devices
  • Both HBM stacks are enabled
  • AXI Switch Global Addressing is enabled
  • A cross stack memory access occurs

When a read or a write command is sent from an AXI port that crosses from one HBM stack to the other through the AXI Switch, the command fails to propagate.  

No error flag or normal response is returned to the AXI port.

The AXI port will ultimately hang as it waits for a response that will never come.

A device that works for some time does not mean that the device is immune to the problem as this can occur with any cross stack transaction.


This behavior is fixed in silicon in production Virtex UltraScale+ HBM devices.

For Engineering Sample devices you can avoid this lockup by not issuing any cross stack transactions.

Both stacks can be enabled and as long as a cross stack transaction does not occur then you will not encounter the hang.

If cross stack transactions are required, use the following work-around:

  1. Apply the attached patch file to the design
    • Patch files are provided for the 2018.2, 2018.3, and 2019.1 Vivado releases
  2. As a result of the changes in the patch file there is a requirement that the AXI Switch Clock for the HBM stack cannot be driven by a BUFG
    • If the AXI Switch Clock (designated in the HBM Configuration Selection page of the HBI IP configuration GUI) is being driven by a BUFG then remove the BUFG from this clock path
  3. As a result of the changes in the path file there is a new clock generated from 1/8th the APB clock that needs to be constrained
    • The default names for these clocks are o_APB_PCLK_by8_st0 and o_APB_PCLK_by8_st1
    • These clocks need the following constraints. Make sure to modify the names to match your design:
set_clock_groups -logically_exclusive -group [get_clocks AXI_ACLK*_st0 ] -group [get_clocks o_APB_PCLK_by8_st0 ]
set_clock_groups -logically_exclusive -group [get_clocks AXI_ACLK*_st1 ] -group [get_clocks o_APB_PCLK_by8_st1 ]

Revision History

11/06/2018Initial release
01/06/2019Updated with 2018.3 patch files
08/23/2019Updated with 2019.1 patch files


Associated Attachments

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69267 Virtex UltraScale+ HBM Controller - Release Notes and Known Issues N/A N/A
AR# 71312
Date 08/23/2019
Status Active
Type General Article
People Also Viewed