AR# 71318

2017.x-2018.2 Zynq UltraScale+ MPSoC: Linux reboot command causing boards to hang when TRACE port is enabled over EMIO

Description

In Vivado 2017.x-2018.2, adding the TRACE port to the Vivado design and routing it to EMIO causes the reboot command in Linux to not work.

The FSBL after reboot hangs when accessing 0XFE980004 (TPIU_CURRENT_PORT_SIZE).

The root problem is that the TPIU requires a running trace clock (in the case where EMIO is coming from the PL) to access CoreSight registers (like TPIU_CURRENT_PORT_SIZE) and after a reboot the PL is cleared, so no clock is provided and the transaction hangs.

Solution

This issue is planned to be fixed in a future release.

In the meantime, the work-around is to modify psu_init as follows:

Move the  following lines from the psu_peripherals_init_data() function in psu_init.c to the end of psu_ps_pl_isolation_removal_data():

PSU_Mask_Write(TPIU_LAR_OFFSET, 0xFFFFFFFFU, 0xC5ACCE55U);
PSU_Mask_Write(TPIU_CURRENT_PORT_SIZE_OFFSET,0x80000000U, 0x80000000U);
PSU_Mask_Write(TPIU_EXTCTL_OUT_PORT_OFFSET,0x000000FFU, 0x00000001U);
PSU_Mask_Write(TPIU_LAR_OFFSET, 0xFFFFFFFFU, 0x00000000U);

 

After this change, the clock from the PL will be available when the FSBL is configuring the TPIU. 

AR# 71318
Date 12/06/2018
Status Active
Type General Article
Devices
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Boards & Kits