This answer record provides a Vivado ILA Usage Guide for UltraScale FPGA Gen3 Integrated Block for PCI Express in a downloadable PDF to enhance its usability.
Answer Records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
PCIe Link training and stability issues make up the vast majority of the issues in interlink connectivity.
The document attached to this answer record describes the use case for debugging these issues in the Xilinx Vivado Design Suite with the integrated tools.
This document will be focused on the use of Vivado ILA for debug by capturing link training debug signals in the UltraScale FPGA Gen3 Integrated Block for PCI Express core.
The document does not go into details on the background of link training issues.
07/24/2018 - Initial release
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