For I, M and Q grade parts, when the QPLL0 is locked at low temperature Tm and ramped up to high Temperature Tn, if Tn-Tm > 110 degrees C, data errors can occur.
This problem will not occur if the temperature ramp Tn - Tm is less than 110 degrees C and it is not dependent on the ramp rate.
This does not impact QPLL1 or CPLL based designs.
Updating QPLL0 attributes will fix this issue.
For GTH, Q- and M-Grade devices in production at the time of this Design Advisory (ZU4EV and ZU5EV only), this issue will be resolved in the UltraScale+ FPGAs Transceivers Wizard release for Vivado version 2018.2.1.
Other GTH and all GTY Q- and M-Grade devices will go into production in 2018.2.1 and later versions and as a result are not affected by this Design Advisory.
For GTH and GTY I-Grade only, this issue will be resolved in the UltraScale+ FPGAs Transceivers Wizard release for Vivado 2018.2.2.
Until then, changing to the following attribute settings will fix this issue:
A Tcl script is attached to this Answer Record that will assist in making these setting changes to the I grade parts for Vivado Versions prior to 2018.2.2.
Unzip the file and follow the instructions in the ReadMe.txt to make these changes.
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