This article is part of the PCI Express Solution Centre(Xilinx Answer 34536) Xilinx Solution Center for PCI Express
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Supported devices can be found in the following locations:
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
The following table provides a list of tactical patches for the UltraScale+ PCI Express 4c Integrated Block core applicable on corresponding Vivado tool versions.
|Answer Record||Core Version (After installing the Patch)||Tool Version|
|(Xilinx Answer 75334)||v1.0 (Rev 75334)||2020.1|
|(Xilinx Answer 73417)||v1.0 (Rev 73417)||2019.2|
|(Xilinx Answer 71498)||v1.0 (Rev 71498)||
Known and Resolved Issues
The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2017.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 75334)||Tactical Patch for Issue Fixes:
||Vivado 2020.1||Not Resolved Yet
Tactical Patch Provided
|(Xilinx Answer 73417)||Tactical Patch for Issue Fixes:
||Vivado 2019.2||Vivado 2020.1|
|(Xilinx Answer 71498)||MCP (Multi Cycle Path) Constraints on RQSEQNUM* signal missing for ES1 parts||Vivado 2018.2||Vivado 2018.3|
|(Xilinx Answer 71375)||Link does not train in Gen1 design with Refclk at 125MHz and 250MHz speeds||Vivado 2018.1||Vivado 2018.2|
|(Xilinx Answer 75490)||Vivado 2020.1.1 - GTYCHK-1 and GTYCHK-2 DRC Violations|