This answer record contains the Release Notes and Known Issues for the UltraScale+ PCI Express 4c Integrated Block Core and includes the following:
This article is part of the PCI Express Solution Centre
Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support.
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Supported devices can be found in the following locations:
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
The following table provides a list of tactical patches for the UltraScale+ PCI Express Integrated Block core applicable on corresponding Vivado tool versions.
|Answer Record||Core Version (After installing the Patch)||Tool Version|
Known and Resolved Issues
The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2017.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 71498)||MCP (Multi Cycle Path) Constraints on RQSEQNUM* signal missing for ES1 parts||v1.3 (Rev3)||Not Resolved Yet|
Tactical Patch Provided
|(Xilinx Answer 71375)||Link does not train in Gen1 design with Refclk at 125MHz & 250MHz speeds||v1.3 (Rev2)||v1.3 (Rev3)|
08/01/2018 - Initial Release
09/05/2018 - Added (Xilinx Answer 71498)