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AR# 71399

UltraScale+ PCI Express 4c Integrated Block - Release Notes and Known Issue

Description

This answer record contains the Release Notes and Known Issues for the UltraScale+ PCI Express 4c Integrated Block Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Xilinx Forums:

Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Solution

Supported devices can be found in the following locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v1.0 (Rev4)2018.3
v1.0 (Rev3)2018.2
v1.0 (Rev2)
2018.1
v1.0 (Rev1)2017.4
v1.02017.3


Tactical Patch

The following table provides a list of tactical patches for the UltraScale+ PCI Express Integrated Block core applicable on corresponding Vivado tool versions.

Answer RecordCore Version (After installing the Patch)Tool Version
v1.3 (Rev3)
2018.2


Known and Resolved Issues

The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2017.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 71498)
MCP (Multi Cycle Path) Constraints on RQSEQNUM* signal missing for ES1 partsv1.3 (Rev3)Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 71375)Link does not train in Gen1 design with Refclk at 125MHz & 250MHz speedsv1.3 (Rev2)
v1.3 (Rev3)


Other Information:

NA

Revision History:

08/01/2018 - Initial Release

09/05/2018 - Added (Xilinx Answer 71498)

AR# 71399
Date 02/14/2019
Status Active
Type Release Notes
IP
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