AR# 71399

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UltraScale+ PCI Express 4c Integrated Block - Release Notes and Known Issue

Description

This answer record contains the Release Notes and Known Issues for the UltraScale+ PCI Express 4c Integrated Block Core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Xilinx Forums:

Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Solution

Supported devices can be found in the following locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Tactical Patch

The following table provides a list of tactical patches for the UltraScale+ PCI Express 4c Integrated Block core applicable to corresponding Vivado tool versions.

Answer RecordCore Version (After installing the Patch)Tool Version
(Xilinx Answer 76779)v1.0 (Rev 76779)2021.1
(Xilinx Answer 76337)v1.0 (Rev 76337)2020.2
(Xilinx Answer 75835)v1.0 (Rev 75835)2020.1
(Xilinx Answer 75334)v1.0 (Rev 75334)2020.1
(Xilinx Answer 73417)v1.0 (Rev 73417)2019.2
(Xilinx Answer 71498)v1.0 (Rev 71498)
2018.2

Known and Resolved Issues

The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2017.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 76779)Tactical Patch for Issue Fixes:
  • Added MCP 4 on CFGPHYLINKDOWN
Vivado 2021.1Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 76337)MSI-X Table Size support for more than 8 vectorsVivado 2020.2Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 75835)get_timing_arcs command results in '0' for PCIe hardblock in VU19P devicesVivado 2020.1Vivado 2020.2
(Xilinx Answer 75334)Tactical Patch for Issue Fixes:
  • Bug Fix: Fixed VU19P device support issue
Vivado 2020.1Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 73417)Tactical Patch for Issue Fixes:
  • CPLL fails to lock in when reference clock is set to 250MHz at Gen1 rate with PCIe IP
Vivado 2019.2Vivado 2020.1
(Xilinx Answer 71498)MCP (Multi Cycle Path) Constraints on RQSEQNUM* signal missing for ES1 partsVivado 2018.2Vivado 2018.3
(Xilinx Answer 71375)Link does not train in Gen1 design with Refclk at 125MHz and 250MHz speedsVivado 2018.1Vivado 2018.2

Other Information:

(Xilinx Answer 75490)Vivado 2020.1.1 - GTYCHK-1 and GTYCHK-2 DRC Violations

Revision History:

  • 08/01/2018 - Initial Release

Linked Answer Records

Child Answer Records

AR# 71399
Date 08/19/2021
Status Active
Type Release Notes
IP
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