General Description: How do I infer ROM for Virtex, Virtex-E and Virtex-II?
FPGA Express versions 3.3 and above have the ability to infer ROM primitives for Virtex designs if the syntax described below is used. Three points must be noted:
1. Be sure to define at least 75% of the states. (50% of the states may be defined if the "infer_mux" attribute is used.)
2. These components will be written into the EDIF netlist as LUT4s, not ROM16X1s. Either one will be implemented identically.
3. This feature is only applicable to Virtex-based architectures.
Currently, FPGA Express can not infer RAM.
Beginning with FPGA Express 3.5 for Virtex, Virtex-E, and Virtex-II, block RAM for ROMs (rather than LUTs) will be inferred in the following cases:
For Virtex and Virtex-E: Block RAM will be inferred when the address line is at least 10 bits, and the data line is 3 bits or greater. Also, block RAM will be inferred when the address line is 11 or 12 bits; no minimum data width is required.
For Virtex-II: Block RAM will be inferred for ROM if the address line is between 10 to 14 bits; no minimum data width is required.