When targeting a -2LI device in the Zynq UltraScale+ RFSoC family, I do not get DRC errors when placement and FMAX guidelines are not followed as shown in the SD-FEC product guide. (PG256)
Why does this occur, and how can possible design issues be avoided?
This is a known issue in SDFEC v1.1 (Rev 1) in the 2018.2.1 release, it will be fixed in 2018.3 and later versions.
The -2LI devices were added to the Zynq UltraScale+ RFSoC family in the 2018.2.1 Vivado release.
However, SD-FEC DRC checks were not updated for the new speed grade and so will not get flagged if the design rules outlined in the product guide are not followed when using the -2LI devices.
To ensure successful design implementations, refer to the Soft-Decision FEC Integrated Block v1.1 Product Guide, and ensure that your design follows the Placement Location Guidelines and FMAX rules for the SD-FEC IP Core.
For a list of known issues for the Soft-Decision FEC (SDFEC) Integrated Block, see (Xilinx Answer 70720)
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 70720 | Soft-Decision FEC (SDFEC) Integrated Block - Release Notes and Known Issues for Vivado 2018.1 and newer tool versions Article | N/A | N/A |
| AR# 71415 | |
|---|---|
| Date | 08/14/2018 |
| Status | Active |
| Type | Known Issues |
| Tools | |
| IP | |