AR# 71416

2018.1/2 Zynq UltraScale+ MPSoC: How to get baremetal DPDMA example to work with single lane DisplayPort configured.

Description

On a Zynq UltraScale+ MPSoC device how can I get the bare metal DPDMA example to work with single lane DisplayPort configured.

Solution

Below are the steps you need to follow.

  1. Create a standalone BSP project using ZCU102 HDF and then change the psu_dp to dppsu as mentioned in the wiki http://www.wiki.xilinx.com/ZynqMP+Standalone+DisplayPort+Driver Test Procedure section.
    By default, psu_dp is set to avbuf by the SDK.



  2. Open the MSS file and then export the DPDMA example.




  3. Import the DPDMA example files.

  4. In xdpdma_video_example.c, modify RunCfgPtr->LaneCount to 'LANE_COUNT_1' and  RunCfgPtr->UseMaxLaneCount to '0' as shown below. 


  5. In xdppsu.c, xpdpsu_hw.h, and xavbuf_clk.c, modify the code as shown below.
    Note: changes to xavbuf_clk.c are required for the 2018.1 release only and this patch is merged into the 2018.2 release.






  6. Build the project, and once the build is completed, create a BOOT.bin using the FSBL, PMUFW and DPDMA example elf.
  7. Run targetting a ZCU102 connected with DisplayPort.
    You should now see a green color on the bottom half of the DisplayPort monitor:
    .

  8. Target console log:
Xilinx Zynq MP First Stage Boot Loader
Release 2018.1   Aug  6 2018  -  10:19:50
DPDMA Generic Video Example Test
HPD event .......... ! Connected.
Lane count =    1
Link rate =     20

Starting Training...
        ! Training succeeded.
DONE!
.......... HPD event
Generating Overlay.....
Successfully ran DPDMA Video Example Test
AR# 71416
Date 08/31/2018
Status Active
Type General Article
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