AR# 71421

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Queue DMA subsystem for PCI Express (Vivado 2018.2) - Tactical patch for issue fixes

Description

Version Found: v2.0

Version Resolved and other Known Issues: (Xilinx Answer 70927)

The tactical patch provided with this answer record contains the following fixes for issues in the Queue DMA Subsystem for PCI Express in Vivado 2018.2.

  1. Descriptor Engine and Prefetch Engine deadlock:
    The QDMA can get into a deadlock situation where the Descriptor Engine stops fetching the descriptors due to the back pressure on tm_sts.
    The Prefetch Engine cannot handle more tm_sts because it is blocked by a descriptor that does not come from the Descriptor Engine.
    The implication is that a single bad actor VF can hang all queues in QDMA.

  2. Completion Timers Issue:
    When a lot of queues are running with a timer based trigger mode, it can lead to some of the timers never expiring.
    This will lead to those C2H queues stalling indefinitely.

  3. Eviction of Prefetch Descriptors Issue:
    With prefetch enabled, eviction of prefetched descriptors happens improperly.
    This leads to data corruption.

  4. Credit Coalescing Issue:
    The credits to the Descriptor Engine need to be coalesced to keep the fetch rate high.
    The implementation without the fix supports up to 15 simultaneous queues but if more than 15 queues are finely interleaved, the performance drop is large for small packets.

  5. C2H QID0 Issue:
    When a queue invalidation or certain descriptor error events are reported from the Descriptor Engine to the Prefetch Engine, it can result in it getting recorded against QID0 instead of the actual QID.
    This would result in packet drop on QID0.

  6. Outstanding data based request throttling in Streaming H2C Engine:
    When the Streaming H2C Engine has a significant amount of data outstanding from the PCIe side, it can fill up the buffer in RQ block which can impact C2H Stream performance.
    A new SW visible register has been added to program this outstanding data threshold as seen by the H2C Streaming Engine.
    When this threshold is reached, the H2C Streaming Engine stops sending more read requests until some data gets issued to User logic, thus reducing the amount of outstanding data.
    The register also includes a disable for this feature. The new register is at 0xE24 and has the following format:
     


  1. User+Timer+Count trigger mode in C2H Completion Engine:
    A new trigger mode has been added to moderate interrupts and status writes from the C2H Completion Engine.
    This mode is sensitive to User provided trigger, expiring timers as well as the count of unread Completions in the C2H Completion Ring.
    The new mode can be programmed in the C2H Completion Context's existing trig_mode field by setting it to 0x5.

This patch contains all previously released fixes for the 2018.2 version, detailed in (Xilinx Answer 70927)



This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This issue will be fixed in the next release of the core.

Please install the patch in Vivado 2018.2 as described in the readme file included in the patch zip file.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

08/29/2018 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
AR71421_Vivado_2018_2_preliminary_rev1.zip 6 MB ZIP
AR# 71421
Date 08/29/2018
Status Active
Type Known Issues
IP
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