The following DRC is triggered during opt_design if you have a dedicated reset routing enabled in the AXI Bridge for PCI Express Gen3 core and you drive logic into sys_rst.
This example has a LUT1 driving the sys_rst port with the dedicated reset routing enabled.
This issue applies to the AXI Bridge for PCI Express Gen3 / UltraScale FPGA Gen3 Integrated Block for PCI Express / DMA Subsystem for PCI Express.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
When the core is in "Basic Mode" and you are using a PCIe Block Location that supports Tandem, dedicated reset routing is turned on by default.
The recommended guideline is as follows:
In the core configuration GUI, uncheck "Use dedicated PERST routing Resources"
09/03/2018 - Initial release