AR# 71453


Queue DMA subsystem for PCI Express (PCIe) - Performance Report


This answer record provides QDMA Performance Report in a downloadable PDF to enhance its usability. 

Answer Records are Web-based content that are frequently updated as new information becomes available.

Visit this answer record to obtain the latest version of the PDF.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


The Xilinx QDMA (Queue Direct Memory Access) Subsystem for PCI Express (PCIe) is a high-performance DMA for use with the PCI Express 3.x Integrated Block(s).

It can work with AXI Memory Mapped or Streaming interfaces and uses multiple queues optimized for both high bandwidth and high packet count data transfers. (Please refer to (PG302) QDMA Subsystem for PCI Express v4.0 for additional details).
Xilinx provides two reference drivers for QDMA IP:

  • Linux Kernel driver (Linux Driver)
  • DPDK Poll Mode driver (DPDK Driver)

This performance report provides the measurement of the DMA bandwidth of the QDMA IP using the reference Linux and DPDK drivers. 

This report provides the measured DMA bandwidth with different DMA configurations that can be extrapolated to a target application.  
The reference design is targeted at a PCIe Gen 3 x16 design on a Xilinx Virtex UltraScale+ FPGA VU9P device on a VCU1525 board. The reference design can also be ported to other Xilinx cards.
Note: The QDMA DPDK Driver and Linux Driver are available in (Xilinx Answer 70928)

Revision History:

  • 08/27/2018 - Initial Release
  • 10/05/2018 - Added Linux Driver performance report and updated DPDK performance report
  • 12/10/2018 - Updated performance report 
  • 02/25/2019 - Performance report update
  • 11/08/2020 - Performance report update with QDMA v4.0




Associated Attachments

AR# 71453
Date 12/09/2020
Status Active
Type General Article
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