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AR# 7148

V2.1i COREGEN, VIRTEX: Problems with synchronous control signal (SCLR, SINIT) HDL behavioral modelling in the LD-Based LATCH module

Description

Keywords: vhdl, verilog, coregen, latch

Urgency: standard

General Description:
When generating a CORE Generator LD-base LATCH module, if
the user requests the synchronous SSET and/or SCLR pins plus a
GE pin, but no asynchronous control pins, the VHDL and Verilog
behavioral models do will respond correctly to an 'X' driving the SSET
and/or SCLR pins.

The current behavior is that

1. if SCLR is unknown ("X"), and the Data input is "1", the output is
"1" instead of "X".

2. if SSET is unknown ("X"), and the Data input is "0", the output is
"0" instead of "X".

The other problem associated with these pins is that the modelling of
power-on should NOT be affected by the presence of the synchronous
control pins.

The problem behavioral models are:

VHDL: c_reg_ld_v1_0.vhd, version 1.1.2.13
Verilog: C_REG_LD_V1_0.v, version 1.1.2.11


Solution

1

VHDL: This problem has been fixed in the C_IP2 release.

If you do not have access to this update, you can
make the required modfications manually as follows:

The following changes need to be made in the c_reg_ld_v1_0.vhd model:

Lines 68-69:
ge1_1 : if ((C_HAS_ACLR = 1) or (C_HAS_ASET = 1) or (C_HAS_AINIT = 1))
and ((C_HAS_SCLR = 1) or (C_HAS_SSET = 1) or (C_HAS_SINIT = 1))

Change to:
ge1_1 : if ((C_HAS_SCLR = 1) or (C_HAS_SSET = 1) or (C_HAS_SINIT = 1))



Lines 73-74:
ge1simple : if (C_HAS_GE = 1) and not(((C_HAS_ACLR = 1) or (C_HAS_ASET = 1) or (C_HAS_AINIT = 1))
and ((C_HAS_SCLR = 1) or (C_HAS_SSET = 1) or (C_HAS_SINIT = 1))

Change to:
ge1simple : if (C_HAS_GE = 1) and not(((C_HAS_SCLR = 1) or (C_HAS_SSET = 1) or (C_HAS_SINIT = 1))



Lines 143-148 should be removed or commented out:
elsif (C_HAS_SCLR = 1) then

intQ <= (others => '0');
elsif (C_HAS_SSET = 1) then
intQ <= (others => '1');
elsif (C_HAS_SINIT = 1) then
intQ <= SIV;

Change to:
-- elsif (C_HAS_SCLR = 1) then
-- intQ <= (others => '0');
-- elsif (C_HAS_SSET = 1) then
-- intQ <= (others => '1');
-- elsif (C_HAS_SINIT = 1) then
-- intQ <= SIV;

2

Verilog:

The following changes need to be made in the C_REG_LD_V1_0.v model

Line 72-73:

assign intGE = ((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) &&
(C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) &&
Replace with:
assign intGE = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) &&




Lines 100-105:

else if(C_HAS_SCLR === 1)
#1 data = `all0s;
else if(C_HAS_SSET === 1)
#1 data = `all1s;
else if(C_HAS_SINIT === 1)
#1 data = SIV;

Remove this block of code, or comment it out as follows:

// else if(C_HAS_SCLR === 1)
// #1 data = `all0s;
// else if(C_HAS_SSET === 1)
// #1 data = `all1s;
// else if(C_HAS_SINIT === 1)
// #1 data = SIV;
AR# 7148
Date Created 07/30/1999
Last Updated 08/01/2001
Status Archive
Type General Article