Version Found: DDR4 2018.2, v2.2 (rev 5), DDR3 2018.2 V1.4 (Rev 5)
Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3
DDR4 or DDR3 multi rank memory interfaces using the Self Refresh Save Restore feature with FPGA Reconfiguration might encounter post restore multi-bit ECC errors.
The ECC errors result from incorrect restoration of PHY ODELAY registers.
The restoration logic loads the PHY ODELAY register with tap values for the rank that did not match the rank pointer.
This results in incorrect writes to the DRAM causing multi-bit ECC errors.
The fix for this issue is provided in the Vivado 2018.3 release.
Patches for earlier versions of Vivado will be added to this Answer record when available.
For immediate support, please contact Xilinx Technical Support.
Revision History
09/10/18 - initial release
| Name | File Size | File Type |
|---|---|---|
| AR71531_Vivado_2016_4_preliminary_rev3.zip | 5 MB | ZIP |
| AR71531_Vivado_2018_1_preliminary_rev1.zip | 4 MB | ZIP |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 69036 | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues | N/A | N/A |