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AR# 7158

FPGA Express - VHDL Error: "Range 'U' to 'X' (or 'Z' to '-') not covered by choices. (VSS-838)"


Keywords: 1.5, 1.5i, Foundation, 3.1, 3.2, Express, range, not, covered, VSS, 838, VSS-838, mux,
multiplex, multiplexer, VHDL

Urgency: Standard

General Description:
I am checking the syntax of a VHDL code block for inference of a multiplexer; when the
port is defined as:


and the code within the process statement is:

case MUX_CTRL is
when '0' =>
when '1' =>
end case;

FPGA Express gives the following error:

Error: Range 'U' to 'X' not covered by choices. (VSS-838) (FE-dm-hdlc-unknown)
Error: "Range 'Z' to '-' not covered by choices. (VSS-838) (FE-dm-hdlc-unknown)


This occurs because not all possible values of STD_LOGIC were covered by the case statement.
There are values possible for STD_LOGIC other than simply "0" and "1" (e.g., "U", "X", and "Z")
that need to be covered. To do this, simply add the following to the end of the case statement:

when others => null;

Preferably, this will take the place of the last comparison in the case statement.

The following is the case statement code given in the HDL Editor Language Assistant:

case <expression> is
when <choices> =>
when <choices> =>
when others =>
end case;
-- example:
--case SEL is
-- when 0 | 1 | 2 =>
-- Z <= B;
-- when 3 to 10 =>
-- Z <= C;
-- when others =>
-- null;
--end case;
AR# 7158
Date 08/11/2003
Status Archive
Type General Article