AR# 71599

UltraScale/UltraScale+ DDR3/DDR4 Memory IP - How to Create a Pinout that Supports x4, x8, and x16 Memory Devices

Description

In order to be compatible with a wide variety of memory solutions, especially for flexible DIMM device support, it is necessary to consider an FPGA pinout that can support x4, x8, and x16 memory devices.

This Answer Record will describe how to assign the individual signals within an FPGA Byte Lane that is compatible with x4, x8, and x16 memory devices.

The advantage of a pinout like this is that you can target one type of DIMM device at launch and if a larger device is required, or the existing device goes End of Life you can reconfigure the IP for the new part, even if the native components were x8 devices but are now x4 devices.

Solution

General Guidance:

Before starting, please review the PCB Guidelines for DDR3 and DDR4 in (UG583), and also review the DDR3/DDR4 Pin and Bank Rules in (PG150):

(UG583) - UltraScale Architecture PCB Design User Guide

(PG150) - UltraScale Memory Product Guide

The specific requirements for the FPGA Byte Lane that drive the final pinout that supports x4, x8, and x16 devices are covered in detail in the Pin and Bank Rules found in (PG150).

Byte Lane Assignments for a x4, x8, and x16 Compatible Pinout:

In order for the FPGA Byte Lane to support x4, x8, and x16 with a common pinout, there are multiple requirements discussed in the Pin and Bank Rules section of (PG150) that must be met. 

These dependencies are related to the type of I/O available in the FPGA Byte Lane and how this relates to calibration and DDR3/DDR4 protocol. 


The big difference between x4 memory devices and x8 and x16 memory devices is that x4 DDR3 devices do not have a Data Mask (DM) pin, and for x4 DDR4 devices they do not have the Data Mask and Data-Bus Inversion pin (DM_n/DBI_n). 

For x8 and x16 DDR3 devices it is always expected that the DM pin is routed from the FPGA to the memory device.

For x8 and x16 DDR4 devices, regardless of the Data Mask and DBI setting in the IP, it is always expected that the DM_n/DBI_n pin is routed from the FPGA to the memory device.

Additionally, when targeting x4 memory devices, there are now 4-bits of data for every DQS pair, which means that a single FPGA Byte Lane will have two nibbles of 4-bits of data plus their respective DQS pair. 


There are certain requirements placed on the DM and DM_n/DBI_n pins which limit their placement in an FPGA Byte Lane. 

Related to this are requirements for the Data Strobes (DQS) pins for DDR3/DDR4 devices that limit their placement in an FPGA Byte Lane. 

There is only one possible assignment for these signals within an FPGA Byte Lane that will satisfy these requirements for the DM and DM_n/DBI_n pins as well as the DQS pin placements, for x4, x8, and x16 device configurations.

Below is the FPGA Byte Lane view that shows a pinout compatible with x4, x8, and x16 DDR3 devices:


 

Note the placement on the DM0 signal on the N0 pin of the FPGA Byte Lane as well as the DQS assignments. For x8 and x16 device configurations there is only one pair of DQS pins for every 8-bits of data. 

For these types of configurations, the expected DQS pair is the DQS0_n and DQS0_p pins at N6 and N7 of the FPGA Byte Lane. Because x8 and x16 devices have the DM signal, it is assigned to the N0 pin of the FPGA Byte Lane.

When targeting x4 memory components, you now have two pairs of 4-bits of data, two pairs of DQS pins, and no DM pin. For the x4 configuration the second DQS pair is noted by the DQS9_p and DQS9_n signals located on the N0 and N1 pins of the FPGA Byte Lane.

Also notice that the data bits for the lower nibble are denoted by the DQ[3:0] grouping placed at pins N8-N11 and are associated with the DQS0 strobe at pins N6 and N7. 

The upper nibble is denoted by the DQ[7:4] grouping placed at pins N2-N5 and are associated with the DQS9 pair at pins N0 and N1. It is critical that the 4-bit nibbles are assigned in this manner in order for calibration to work with x4 configurations. 

The specific data bits within the nibble can be swapped with any other data bits of that nibble. You cannot swap across the two nibbles if you want to be compatible with x4 devices.

Below is the FPGA Byte Lane view that shows a pinout compatible with x4, x8, and x16 DDR4 devices:


 

The DDR4 FPGA Byte Lane pin assignment to support a common x4, x8, and x16 layout follows the same rules as the DDR3 FPGA Byte Lane Assignment. 

The expected DQS for x8 and x16 devices is DQS0_t and DQS0_t placed at N6 and N7 and the DM0/DBI0 pin is placed at N0. 

When targeting x4 devices there are two pairs of 4-bit nibbles, two DQS pairs, and no DM0/DBI0 pin. The second DQS pair is DQS9_t and DQS9_t placed at N0 and N1 of the FPGA Byte Lane.

The same rules apply for swapping data bits within nibbles. In order to be compatible with x4 devices you cannot swap data bits across the two nibbles.

Pin Mapping for x4 DIMM Devices:

Another point of confusion regarding x4 memory pinouts is the assignment of the DQS pairs and data bits generated by the FPGA tools to those of the actual memory device on the board.

The figure below shows the mapping of a 72-bit DDR3 interface that is targeting x4 components to the memory data sheet:


 

The figure below shows the mapping of a 72-bit DDR4 interface that is targeting x4 components to the memory data sheet:


 

It might not be immediately clear from looking at it, but if you have followed the FPGA Byte Lane assignments for x4, x8, and x16 support, and also followed the DQS assignments from the XDC to the memory data sheet, then you will have a single board layout and FPGA pinout that is compatible with x4, x8, and x16 memory devices.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A
AR# 71599
Date 11/09/2018
Status Active
Type General Article
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IP