General Description: What format netlist must I produce when using Synopsys products? What choices do I have?
Virtex designs require EDIF netlists; XNF is not supported. When using FPGA Compiler or Design Compiler, only generate a .SEDIF file. FPGA Express / Compiler II will produce a .EDF file.
For non-Virtex devices (3k, 4k, 5k, Spartan, 9k), Design Compiler will produce EDIF (.SEDIF) only, and FPGA Compiler will produce XNF (.SXNF) only. FPGA Express / Compiler II will produce XNF files for these families, but will produce EDIF in a future release (version 3.4).