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AR# 71680

VCU1525 - Unexpected behavior on QSFP0/QSFP1 and USER_SI570 clocks


On some VCU1525 boards, it has been seen that QSFP0/QSFP1 clocks come up at 161MHz and not the documented 156.25MHz clock.

In addition, the USER_SI570 clock is not toggling.


In order to use the 156.25MHz QSFP0/QSFP1 rate, the user needs to drive the two QSFP#_FS[1:0] pins appropriately, and then issue a QSFP0_REFCLK_RESET.

Alternatively, the MGT_SI570_CLOCK0 pin (connected to FPGA PIN M11 on MGTREFCLK0 in Quad 231) can be used. 

This powers on to 156.25MHz and does not require any GPIO to configure its rate.

Instead of using the USER_SI570 clock, the 300MHz clock can be fed to an MMCM, or MGT_SI570_CLOCK0 can also be fed from IBUFDS_GT -> BUFG.

Linked Answer Records

Master Answer Records

AR# 71680
Date 11/01/2018
Status Active
Type General Article
Boards & Kits
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