AR# 71744

HW-SYSMON - UltraScale - When I2C capable pins in Master and Slave SLRs are used as input or bidirectional pins, it can disrupt SYSMON operation and activate the low driver legs of the IOB, disrupting the user I/O function of the pins.

Description

Each SLR has a pair of dual-purpose I2C capable pins connected to the SYSMONE1 block. 

When both I2C capable pins in an SLR are used as fabric input or bi-directional pins, transitions on these pins can inadvertently activate the I2C interface. 

This can cause the following behavior:

  • User Data can be driven low on these pins by the I2C interface
  • SYSMON configuration can be corrupted

If the I2C interface is activated, the user I/O functionality on these pins is disrupted and can force the pins to be driven low by the drivers on these IOB.

Solution

The I2C controller in the SYSMONE1 block has a direct connection to dual purpose I2C capable input pins in each SLR that cannot be disabled when these pins are used in the design to receive data (i.e. input or bi-directional user operation).

A list of the affected pin pairs are attached to this Answer Record.

If both pins toggle, the incoming data on these pins could potentially look like a valid I2C transaction to the SYSMONE1 and could modify the SYSMONE1 configuration registers. 

 

High-speed data (greater than 400KHz) that is not intended to look like an I2C transaction, can present itself as an I2C transaction to the SYSMONE1 due to internal filtering circuitry.

A valid I2C sequence typically operates at 400KHz or lower and will include a valid I2C address as well as a DRP command to interface with the SYSMONE1s configuration registers.

In designs that use the SYSMONE1, and use both pins in a pair as an input/bidirectional, the JTAGMODIFIED signal can be used to identify if a write has occurred to the SYSMONE1 from the I2C interface.

Because there is no way to disconnect the I2C controller from the pins, it is recommended that at least one of these pins not be used as active input or bi-directional pins.

 

If the pins are used in an I2C interface without the SYSMONE1 acting as a slave, the I2C address override bit I2C_OR for the SYSMONE1 (bit 15 in config register 0x43) can be set to an appropriate 7 bit address that is not used in the system in order to avoid this issue.

In designs where the SYSMONE1 is NOT used in an SLR, the SYSMONE1 block can be completely disabled to ensure correct I/O operation by applying one of the following two methods:

1) Apply Tcl commands for each SLR's SYSMON:

 

create_cell -reference SYSMONE1 disable_SLR
place_cell disable_SLR SYSMONE1_X0Y0/SYSMONE1
set_property INIT_42 16'h0003 [get_cells disable_SLR]
set_property INIT_74 16'h8000 [get_cells disable_SLR]

2) A SYSMON instance can be instantiated in the HDL with INIT_42 set to 16'h0003 and INIT_74 set to 16'h8000.

Setting these two registers will disable the SYSMONE1 block completely.

Note: The DCLK input of the unused SYSMON should be disconnected or stopped for the register settings to take affect. 

 

Note: See the attached file to determine pin pairs and the appropriate SYSMONE1 location.  

The "SYSMONE1_X0Y0" string in the above example can be replaced with the appropriate SYSMONE1 location for devices with multiple SLRs.

Each SLR can potentially be impacted by this issue so up to three sets of commands might be required to completely disable the SYSMONE1.

Not all devices have multiple SLRs and not all devices with multiple SLRs have relevant pins bonded out.

If a device has multiple pin pairs listed, each pin pair can potentially be impacted by this issue.

Attachments

Associated Attachments

Name File Size File Type
AR71744.csv 1 KB CSV
AR# 71744
Date 07/02/2020
Status Active
Type General Article
Devices