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AR# 7180

Virtex - How do I convert an existing XC4000 or Spartan design to a Virtex design?

Description

What do I need to consider when converting an existing XC4000 or Spartan design to a Virtex design?

Solution

Converting an existing XC4000 design to a Virtex design is a challenging task and you need to be aware of the following: 

 

For schematic-based designs: 

 

- Any XC4000 arithmetic schematic components in XC4000 families cannot be used in Virtex designs because of carry chain differences. This includes adders, subtractors, comparators, counters, large size AND, OR gates, etc. 

 

NOTE: For Viewlogic schematics, if there is a Virtex library component for that arithmetic function in the XC4000 family, you can change the library alias from the XC4000 family to the Virtex library alias, and run the Altran utility. For more information on Altran, see the Viewlogic Interface Guide. To access this guide, go to the following Web page and select 2.1i Software Manuals: 

http://www.xilinx.com/support/software_manuals.htm
 

- Global buffer usage is different. IBUFGs must be used before BUFG if the clock comes in from an external source. 

- Be careful with cores that worked in XC4000; they might not work in Virtex because of architectural differences. Arithmetic cores will definitely not work. 

- Some RPMs (RLOCs, H_SET, U_SET) will not work in Virtex. 

- The Virtex library contains components that the XC4000 families do not contain, such as Block RAMs, SRL16, synchronous SET, RESET FFs, etc, You might want to take advantage of these new components. 

- There are also XC4000 specific components that Virtex does not contain, such as FDSRE, WAND, DECODE, etc. You might need to change them or redesign the logic. 

- Virtex does not contain IFD and OFD components that the XC4000 families contain. To effectively push the flip-flops in the I/O blocks, you can use IOB=True attributes, or the -pr b option when running MAP. For detailed information, see the Constraints Guide, which is accessible at: 

http://www.xilinx.com/support/software_manuals.htm

 

For HDL-based designs: 

 

- If the codes are written in pure RTL, you can simply retarget your design to Virtex and resynthesize them. 

- If there are cores instantiated in your design, some cores will not work in Virtex, especially the arithmetic cores, such as adders, multipliers, etc. 

- For any other instances, make sure the components exist in the Virtex family and that the functionalities are the same. Otherwise, you must find the corresponding components in Virtex and instantiate them. 

- Take advantage of Block RAM, SRL16, CLKDLL or any other Virtex specific components.  

- Global clock buffer usage is different. BUFGs must be used for clocks only. Use IBUFG in front of the BUFG if the clock comes in from the external source.  

- Virtex has no IOB register primitives. You must use the -pr option in MAP or use the IOB=true attribute.  

- The use of FMAP cells should be discontinued. To place a particular function in a Look-Up-Table, simply instantiate a LUT and add an EQN property or INIT values to it. 

- IPAD, OPAD, and IOPAD cells: 

The Unified Library for the XC4000X series has defined these cells as external connection points. The use of the cells is inappropriate for HDL-based designs for board level test cases and should be removed from your design. The output of these cells should be brought to the top level of your design as an input, output, or bi-directional port.

AR# 7180
Date Created 08/21/2007
Last Updated 05/14/2014
Status Archive
Type General Article